UPD16602N NEC, UPD16602N Datasheet - Page 6

• Manufacturer Part Number: UPD16602N
• Description: 312-OUTPUT TFT-LCD FULL COLOR DRIVER
• Manufacturer: NEC

4. NOTES ON USE
6
(1) In order to prevent latch up breakdown, power should be applied in the order of:
(2) V
(3) Likewise, to prevent the sample & hold characteristics from deteriorating, insert a bypass capacitor of 0.1 F
(4) When LPC
(5) Data input/output relationship
(6) Bias control method
Normal operation is assured with approximately 10 k
this, please set LPC
V
order.
This order should also be observed in transition periods.
externally.
Do not share the sample & hold ground V
the edge to the signal board. There is a possibility of high-voltage or logic type noise being superimposed
onto the sample & hold circuit, damaging the analog characteristics (output deviation, etc.).
between V
supply may cause a driver through current, preventing the output range of the output buffer from being
sufficiently secured.
evaluation.
negative feedback, and when the LCD panel load is small, the output voltage may become abnormal.
As shown below, irrespective of right shift and left shift.
Externally applying a voltage to pins BIAS
this case, the analog characteristics (output deviation, driving capability, response speed, etc.) will not
change. Please refer to the configuration in the figure below for the actual circuit. Also refer to the same
configuration for the V
Output
DD1
SS1
Data
, V
SS2(D)
logic input
DD1
D
S
, V
R0
1
“H”, stable current supply of the output buffer may be shut off, which will impede normal
and V
SS2(A)
SS1
D
and V
S
V
COM
B0
“L”.
2
Therefore, determine the capacitance of the bypass capacitor after a thorough
DD2(D), (A)
, and approximately 0.1 F between V
100 A
voltage input circuit. Current per driver IC is as follws.
(per IC)
SS2(C)
D
S
G0
MIN.
3
are connected in the diffusion layer, but also be sure to connect them
V
BIAS1,2
D
S
R1
4
SS2(C)
, V
1
V
and BIAS
DD2
COM
with other ground wiring on the mount board, but connect it to
D
S
B1
5
analog display signal input, and turned off in the reverse
2
can control the output buffer current consumption. In
+ 50 pF, but when the time constant is smaller than
D
S
G1
6
0.01 F
DD2(D), (A)
V
BIAS1
and V
, V
BIAS2
S
D
309
G2
, V
SS2(D), (A)
COM
S
D
310
R3
. An unstable power
S
D
311
B3
PD16602
S
D
312
G3