UPD16435A NEC, UPD16435A Datasheet - Page 4

• Manufacturer Part Number: UPD16435A
• Description: DOT MATRIX LCD CONTROLLER/DRIVER
• Manufacturer: NEC

4
PIN DESCRIPTIONS
Pin Name
COM1 to
SEG1 to
SEG119
D
COM73
RESET
TEST1
TEST2
BUSY
SYNC
OSC
OSC
OSC
0
SCR
WR
WS
RD
CS
RS
to D
1
2
3
7
212 to 176
137 to 171
41 to 70
Pin No.
81 to 134
3 to 38
255
254
253
252
251
250
243
240
242
241
239
235
234
233
238
237
to
Input (Schmitt)
Input (Schmitt)
Input (Schmitt)
Input/Output
Input/output
Input/output
Output
Output
Output
Output
Output
Input
Input
Input
Input
–––
Nch open-drain
Nch open-drain
CMOS 3-state
Analog switch
Analog switch
Output Type
CMOS
–––
–––
–––
–––
–––
–––
–––
–––
–––
Chip select signal
Register selection signal (specifies address register when “0”,
control register when “1”).
Read enable signal. Reads write address when scrolling.
Active edge is falling edge.
Write enable signal.
Active edge is falling edge.
Word length selection signal (4-bit input when “1”, 8-bit input
when “0”).
Transmit/receive data (3-state bidirectional)
Upper
Lower
of 4-bit data).
In test mode, these pins are output pins.
In a 4-bit transfer, storage is performed in the upper (MSB) in
order from the data transferred first.
“0” indicates busy state.
“0”
performed. Output is fixed at V
Signal is output to CPU on completion of one-character scroll.
Synchronization signal input/output pins for master/slave
operation.
externally. Leave the OSC
level.)
resonator is connected. Input the external clock to OSC
2 Hz external clock input pin. Scaled by 2 internally to generate 1
Hz, used as blink synchronization signal.
Common output signals
Segment output signals
“1”
“0” or open
PD16435: Input the 4.19 MHz reference clock to the OSC
PD16435A: This is the pin to which the 4.19 MHz crystal
Initialization of all internal registers and commands is
Test mode
D4 to D7
D0 to D3 (These pins should be set as unused in case
Normal operating mode
2
Description
pin open. (Always outputs high
1
.
PD16435, 16435A
1
first.
1
pin