UPSD3234AV-24U1T STMicroelectronics, UPSD3234AV-24U1T Datasheet - Page 123

• Manufacturer Part Number: UPSD3234AV-24U1T
• Description: Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM
• Manufacturer: STMicroelectronics

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Port Data Registers
The Port Data Registers, shown in Table 100, are
used by the MCU to write data to or read data from
the ports. Table
ports having each register type, and MCU access
for each register type. The registers are described
below.
Data In. Port pins are connected directly to the
Data In buffer. In MCU I/O Input Mode, the pin in-
put is read through the Data In buffer.
Data Out Register. Stores output data written by
the MCU in the MCU I/O Output Mode. The con-
tents of the Register are driven out to the pins if the
Direction Register or the output enable product
term is set to '1.' The contents of the register can
also be read back by the MCU.
Output Macrocells (OMC). The CPLD Output
Macrocells (OMC) occupy a location in the MCU’s
address space. The MCU can read the output of
the Output Macrocells (OMC). If the OMC Mask
Table 99. Drive Register Pin Assignment
Note: 1. NA = Not Applicable.
Table 100. Port Data Registers
Port A
Port B
Port C
Port D
Data In
Data Out
Output Macrocell
Mask Macrocell
Input Macrocell
Enable Out
Register
Drive
Register Name
Open
Drain
Open
Drain
Open
Drain
NA
Bit 7
(1)
100
shows the register name, the
Open
Drain
Open
Drain
Open
Drain
NA
Bit 6
(1)
A,B,C,D
A,B,C,D
A,B,C
A,B,C
A,B,C
A,B,C
Open
Drain
Open
Drain
Open
Drain
NA
Port
(1)
Bit 5
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
Open
Drain
Open
Drain
Open
Drain
NA
READ – input on pin
WRITE/READ
READ – outputs of macrocells
WRITE – loading macrocells flip-flop
WRITE/READ – prevents loading into a given
macrocell
READ – outputs of the Input Macrocells
READ – the output enable control of the port driver
Bit 4
(1)
Register Bits are not set, writing to the macrocell
loads data to the macrocell flip-flops. See
PLDs, page
OMC Mask Register. Each OMC Mask Register
Bit corresponds to an Output Macrocell (OMC) flip-
flop. When the OMC Mask Register Bit is set to a
'1,' loading data into the Output Macrocell (OMC)
flip-flop is blocked. The default value is '0' or un-
blocked.
Input Macrocells (IMC). The Input Macrocells
(IMC) can be used to latch or store external inputs.
The outputs of the Input Macrocells (IMC) are rout-
ed to the PLD input bus, and can be read by the
MCU. See
Enable Out. The Enable Out register can be read
by the MCU. It contains the output enable values
for a given port. A '1' indicates the driver is in out-
put mode. A '0' indicates the driver is in tri-state
and the pin is in input mode.
Slew
Rate
Slew
Rate
Open
Drain
NA
(1)
Bit 3
PLDs, page
112.
MCU Access
Slew
Rate
Slew
Rate
Open
Drain
Slew
Rate
Bit 2
112.
Slew
Rate
Slew
Rate
Open
Drain
Slew
Rate
Bit 1
Slew
Rate
Slew
Rate
Open
Drain
NA
Bit 0
(1)
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