87C196KS Intel Corporation, 87C196KS Datasheet - Page 33

• Manufacturer Part Number: 87C196KS
• Description: ADVANCED 16-BIT CHMOS MICROCONTROLLER
• Manufacturer: Intel Corporation

87C196KT KS DESIGN CONSIDERATIONS
1 EPA TIMER RESET WRITE CONFLICT
2 VALID TIME MATCHES
3 P6 PIN 4- 7 NOT UPDATED IMMEDIATELY
If the user writes to the EPA timer at the same
time that the timer is reset it is indeterminate
which will take precedence Users should not
write to a timer if using EPA signals to reset it
The timer must increment decrement to the
compare value for a match to occur A match
does not occur if the timer is loaded with a value
equal to an EPA compare value Matches also do
not occur if a timer is reset and 0 is the EPA
compare value
Values written to P6 REG are temporarily held
in a buffer If P6 MODE is cleared the buffer is
loaded into P6 REG x If P6 MODE is set the
value stays in the buffer and is loaded into
P6 REG x when P6 MODE x is cleared Since
reading P6 REG returns the current value in
P6 REG and not the buffer
P6 REG
P6 MODE x is cleared
cannot
be
read
changes to
until unless
4 WRITE CYCLE DURING RESET
5 INDIRECT SHIFT INSTRUCTION
6 PORT 4 ADDRESS BEHAVIOR
system in bus Mode 1 or Mode 2 require an ex-
ternal latch on Port 4 to retain the address during
the data portion of the bus cycle Designs using
If RESET occurs during a write cycle the con-
tents of the external memory device may be cor-
rupted
The upper 3 bits of the byte register holding the
shift count are not masked completely If the shift
count register has the value 32
n
times This should have resulted in no shift taking
place
For bus timing Modes 1 and 2 specified only on
the 87C196KT KS C-step Port 4 does not retain
the address during the data portion of the bus
cycle Designs using an 8-bit external memory
an 8-bit external memory system in the KR or
KR
external latch Designs using 16-bit external
memory systems require an external latch on
both Port 3 and Port 4 in all bus timing modes
e
a
1 3 5 or 7 the operand will be shifted 32
1 Wait bus timing modes do not require an
87C196KT 87C196KS
c
n where
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