87C196JQ Intel Corporation, 87C196JQ Datasheet - Page 23

• Manufacturer Part Number: 87C196JQ
• Description: ADVANCED 16-BIT CHMOS MICROCONTROLLER
• Manufacturer: Intel Corporation

87C196JR D-step (JR-D) and the 87C196JR C-step
(JR-C) For a list of design considerations between
68-lead and 52-lead devices please refer to the
52-lead Device Design Considerations section of
this datasheet Since the 87C196JV JT JQ are sim-
ply memory scalars of the 87C196JR the term ‘‘JR’’
in this section will refer to JV JT JR and JQ ver-
sions of the device unless otherwise noted
The JR-C is simply a 87C196KR C-step (KR-C) de-
vice packaged within a 52-lead package This reduc-
tion in pin count necessitated not bonding-out cer-
tain pins of the KR-C device The fact that these
‘‘removed pins’’ were still present on the device but
not available to the outside world allowed the pro-
grammer to take advantage of some of the 68-lead
KR features
The JR-D is a fully-optimized 52-lead device based
on the 87C196KR C-step device The KR-C design
data base was used to assure that the JR-D would
be fully compatible with the KR-C JR-C and other
Kx family members The main differences between
the JR-D and the JR-C is that several of the unused
(not bonded-out) functions on the JR-C were re-
moved altogether on the JR-D
Following is a list of differences between the JR-C
and the JR-D
1 Port3 Push-Pull Operation
2 V
It was discovered on JR-C that if Port3 is select-
ed for push-pull operation (P34 DRV register)
during low speed I O (LSIO) the port was driving
data when the system bus was attempting to in-
put data It is rather unlikely that this errata would
affect an application because the application
would have to use Port3 for both LSIO and as an
external addr data bus Nonetheless this errata
was corrected on the JR-D
The DC Characteristics section of the Automotive
KR datasheet contains a parameter V
put High Voltage in RESET (BD ports)) which is
specified at V
This specification indicates the strength of the in-
ternal weak pull-ups that are active during and
after reset These weak pull-ups stay active until
the user writes to PxMODE (previously known as
PxSSEL) and configures the port pin as desired
These pull-ups do not meet this V
the JR-C The weak pull-ups on specified JR-D
ports have been enhanced to meet the published
specification of I
OH2
Strengthened
CC
OH2
– 1V min at I
e b
15 A
OH2
OH2
e b
OH2
spec on
15
(Out-
A
87C196KR KQ 87C196JV JT 87C196JR JQ
3 ONCE Mode
4 Port0
5 Port1
Writing to these bits will have no effect
P1 PIN x
P1 REG x
P1 DIR x
P1 MODE x
Register Bits
ONCE mode is entered by holding a single pin
low on the rising edge of RESET
this pin is P5 4 SLPINT The JR-C does not sup-
port ONCE mode since P5 4 SLPINT (ONCE
mode entry pin) is not bonded-out on these de-
vices To provide ONCE mode on the JR-D the
ONCE mode entry function was moved from
P5 4 SLPINT to P2 6 HLDA This will allow the
JR-D to enter ONCE mode using P2 6 instead of
removed pin P5 4
On the JR-C P0 0 and P0 1 are not bonded out
However these inputs are present in the device
and reading them will provide an indeterminate
result
On the JR-D the analog inputs for these two
channels at the miltiplexer are tied to V
Therefore initiating an analog conversion on
ACH0 or ACH1 will result in a value equal to full
scale (3FFh) On the JR-D the digital inputs for
these two channels are tied to ground therefore
reading P0 0 or P0 1 will result in a digital ‘‘0’’
On the JR-C P1 4 P1 5 P1 6 and P1 7 are not
bonded out but are present internally on the de-
vice This allows the programmer to write to the
port registers and clear set or read the pin even
though it is not available to the outside world
However to maintain compatibility with D-step
and future devices it is recommended that the
corresponding bits associated with the removed
pins NOT be used to conditionally branch in soft-
ware These bits should be treated as reserved
On the JR-D unused port logic for these four port
pins has been removed from the device and is
not available to the programmer Corresponding
bits in the port registers have been ‘‘hard-wired’’
to provide the following results when read
(x
(x
(x
(x
e
e
e
e
4 5 6 7)
4 5 6 7)
4 5 6 7)
4 5 6 7)
When Read
On the KR
1
1
1
0
REF
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