87C196JQ Intel Corporation, 87C196JQ Datasheet - Page 22

• Manufacturer Part Number: 87C196JQ
• Description: ADVANCED 16-BIT CHMOS MICROCONTROLLER
• Manufacturer: Intel Corporation

87C196KR KQ 87C196JV JT 87C196JR JQ
87C196KR KQ JV JT JR JQ DESIGN
CONSIDERATIONS
1 EPA Timer RESET Write Conflict
2 Valid Time Matches
3 P6 PIN 4– 7 Not Updated Immediately
4 Write Cycle during Reset
22
application because the application would have
to use Port3 for both LSIO and as an external
addr data bus If an application uses external
memory Port3 should not be selected as push-
pull LSIO
‘‘C’’
‘‘D’’
‘‘V’’
‘‘T’’
Devices can be identified by a special mark fol-
lowing the eight-digit FPO number on the top of
the package The following chart specifies what
these markings are for various device steppings
If the user writes to the EPA timer at the same
time that the timer is reset it is indeterminate
which will take precedence Users should not
write to a timer if using EPA signals to reset it
The timer must increment decrement to the
compare value for a match to occur A match
does not occur if the timer is loaded with a value
equal to an EPA compare value Matches also do
not occur if a timer is reset and 0 is the EPA
compare value
Values written to P6 REG are temporarily held
in a buffer If P6 MODE is cleared the buffer is
loaded into P6 REG x If P6 MODE is set the
value stays in the buffer and is loaded into P6
REG x when P6 MODE x is cleared Since read-
ing P6 REG returns the current value in P6
REG and not the buffer changes to P6 REG
cannot be read until unless P6 MODE x is
cleared
If RESET occurs during a write cycle the con-
tents of the external memory device may be cor-
rupted
e
e
e
e
KR KQ C-step
JR JQ D-step
JV JT A-step
Present on JT A-step devices
Present on C-step devices
Present on JV A-step devices
Present on D-step devices
Device
NOTES
Topside Marking
‘‘C’’
‘‘D’’
‘‘A’’
5 Indirect Shift Instruction
6 P2 7 (CLKOUT)
7 CLKOUT
8 EPA Overruns
9 Indirect Addressing with Auto-Increment
10 JV Additional Register RAM
87C196JR JQ C-step to
JR JQ D-step –or – JV JT A-step
DESIGN CONSIDERATIONS
This section documents differences between the
87C197JV A-step (JV-A) 87C196JT A-step (JT-A)
‘‘Understanding EPA Capture Overruns’’ dated
The upper 3 bits of the byte register holding the
shift count are not masked completely If the shift
count register has the value 32
1 3 5 or 7 the operand will be shifted 32 times
This should have resulted in no shift taking place
P2 7 (CLKOUT) does not operate in open drain
mode
The CLKOUT signal is active on P2 7 during
RESET for the KR KQ JV JT JR and JQ de-
vices Note that CLKOUT is not active on P2 7
in RESET for the KT
EPA ‘‘lock-up’’ can occur if overruns are not han-
dled correctly refer to Intel Techbit
12-9-93 Applies to EPA channels with interrupts
and
EPA CONTROL register set to ‘‘1’’)
For the special case of a pointer pointing to itself
using auto-increment an incorrect access of the
incremented pointer address will occur instead of
an access to the original pointer address All oth-
er indirect auto-increment accesses will note be
affected Please refer to Techbit
Incorrect sequence
ld ax
ldb bx
Correct sequence
ld ax
ldb cx
The 8XC196JV has a total of 1 5 Kbytes of reg-
ister RAM The RAM is located in two memory
ranges 0000h – 03FFh and 1C00h – 1DFFh
overruns
ax
bx
ax
ax
enabled
Results in ax being
incremented by 1 and the
contents of the address
pointed to by ax
loaded into bx
where ax
the contents of the address
pointed to by ax to be
loaded into bx and ax
incremented by 1
(ON RT
i
c
bx Results in
n where n
MC0593
a
1 to be
DB0459
bit
e
in