87C196 Intel Corporation, 87C196 Datasheet - Page 32

• Manufacturer Part Number: 87C196
• Description: CHMOS 16-BIT MICROCONTROLLER
• Manufacturer: Intel Corporation

87C196CA 87C196CB
87C196CA ERRATA
This data sheet was published prior to first available
silicon Consequently there is no known errata at
this time
87C196CA DESIGN CONSIDERATIONS
1 PORT0
On the 87C196CA the analog inputs for P0 0 and
P0 1 have been multiplexed and tied to V
fore initiating an analog conversion on ACH0 or
ACH1 will result in a value equal to full scale (3FFh)
On the CA the digital inputs for these two channels
are tied to ground therefore reading P0 0 or P0 1
will result in a digital ‘‘0’’
2 PORT1
On the 87C196CA P1 4 P1 5 P1 6 and P1 7 have
been removed from the device and is unavailable to
the programmer Corresponding bits in the port reg-
isters have been ‘‘hard-wired’’ to provide the follow-
ing results when read
Writing to these bits will have no effect
3 PORT2
On the 87C196CA P2 3 and P2 5 have been re-
moved from the device and are not available to the
programmer Corresponding bits in the port registers
have been ‘‘hard-wired’’ to provide the following re-
sults when read
32
Register Bits
P1 PIN x
P1 REG x
P1 DIR x
P1 MODE x
(x
(x
(x
(x
e
e
e
e
4 5 6 7)
4 5 6 7)
4 5 6 7)
4 5 6 7)
When Read
REF
1
1
1
0
There-
Writing to these bits will have no effect
4 PORT5
On the 87C196CA P5 1 and P5 7 have been re-
moved from the device and are not available to the
programmer Corresponding bits in the port registers
have been ‘‘hard-wired’’ to provide the following re-
sults when read
Writing to these bits will have no effect
5 PORT6
On the 87C196CA P6 2 and P6 3 have been re-
moved from the device and are not available to the
programmer Corresponding bits in the port registers
have been ‘‘hard-wired’’ to provide the following re-
sults when read
Writing to these bits will have no effect
Register Bits
P2 PIN x
P2 REG x
P2 DIR x
P2 MODE x
Register Bits
P5 PIN x
P5 REG x
P5 DIR x
P5 MODE x
P5 MODE x
Register Bits
P6 PIN x
P6 REG x
P6 DIR x
P6 MODE x
(x
(x
(x
(x
(x
(x
(x
(x
(x
(x
(x
(x
(x
e
e
e
e
e
e
e
e
e
e
e
e
e
3 5)
3 5)
3 5)
3 5)
1 7)
1 7)
1 7)
1)
7)
2 3)
2 3)
2 3)
2 3)
When Read
When Read
When Read
1
1
1
0
1
1
1
0
1
1
1
1
0