83C154 TEMIC Semiconductors, 83C154 Datasheet
83C154
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83C154 Summary of contents
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... In addition as for the TEMIC 80C51/80C52, the stop clock mode is also available. The 80C154 is identical to the 83C154 except that it has no on-chip ROM. TEMIC’s 80C154 and 83C154 are manufactured using SCMOS process which allows them to run from MHz with Vcc = 5 V ...
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... Interface Figure 1. Block Diagram 2 www.DataSheet4U.com MATRA MHS Rev.F (14 Jan. 97) ...
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... Diagrams are for reference only. Package sizes are not to scale MATRA MHS Rev.F (14 Jan. 97) 80C154/83C154 P1.5 P1.6 P1.7 RST RxD/P3.0 80C154/83C154 NC TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 LCC www.DataSheet4U.com 80C154/83C154 NC ALE PSEN P /A15 27 P /A14 26 P /A13 25 Flat Pack P0.4/A4 P0.5/A5 P0.6/A6 P0.7/ ALE PSEN P2.7/A14 P2.6/A13 P2.5/A12 3 ...
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... Port 1 also receives the low-order address byte during program verification. In the 83C154, Port 1 can sink or source three LS TTL inputs. It can drive CMOS inputs without external pullups. 2 inputs of PORT 1 are also used for timer/counter ...
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... The interrupt, serial port, and timer blocks continue to function only with external clock (INT0, INT1, T0, T1). Figure 3. Idle and Power Down Hardware. MATRA MHS Rev.F (14 Jan. 97) 80C154/83C154 XTAL1 Input to the inverting amplifier that forms the oscillator. Receives the external oscillator signal when an external oscillator is used. XTAL2 Output of the inverting amplifier that forms the oscillator, and input to the internal clock generator ...
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... PCON : Power Control Register (MSB) SMOD HPD RPD – GF1 GF0 Symbol Position Name and Function SMOD PCON.7 Double Baud rate bit. When set the baud rate is doubled when the serial port is being used in either modes HPD PCON ...
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... External Power Down Internal Power Down External Figure 4. I/O Buffers in the 83C154 (Ports 1, 2, 3). Stop Clock Mode Due to static design, the TEMIC 83C154 clock speed can be reduced until 0 MHz without any data loss in memory or registers. This mode allows step by step utilization, and permits to reduce system power consumption by bringing the clock frequency down to any value ...
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... Figure 6. External Drive Configuration. Hardware Description Same as for the 80C51, plus a third timer/counter : Timer/Event Counter 2 Timer bit timer/counter like Timers 0 and 1, it can operate either as a timer event counter. This is selected by bit C/T2 in the Special Function Register T2CON (Figure 1). It has three operating modes : “ ...
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... The internal pull-up resistances at ports 1~3 can be set to a ten times increased value simply by software. 32 Bit Mode and Watching Mode The 83C154 has two supplementary modes. They are accessed by bits WDT and T32 of register IOCON. Figure 10 showns how IOCON must be programmed in order to ...
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... WDT T32 SERR Symbol Position T32 IOCON.6 WDT IOCON.7 32 Bit Mode T32 = 1 enables access to this mode. As shown in figure 11, this 32 bit mode consists in cascading TIMER 0 for the LSBs and TIMER 1 for the MSBs Figure 10.32 Bit Timer/counter. T32 = 1 starts the timer/counter and T32 = 0 stops it. ...
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... Figure 13 illustrates the 32 bit COUNTER mode. Figure 12. 32 Bit Counter Configuration. In this mode, T32 = 0 and C/ Before it can make an increment, the 83C154 must detect two transitions on its T0 input. As shown in figure 14, Figure 13. Counter Incrementation Condition. The counter will only evolve if a level 1 is detected during state S5P2 of cycle Ci and if a level 0 is detected during state S5P2 of cycle ...
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... OSC 24. The overflow of the TIMER/COUNTER is signalled by raising flag TF1 to 1. The reset of the 83C154 is executed during the next machine cycle and lasts for the next 5 machine cycles. The results of this reset are identical to those of a hardware reset. The internal RAM is not affected and the special register assume the values shown in Table 3 ...
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... Secret ROM TEMIC offers 83C154 with the encrypted secret ROM option to secure the ROM code contained in the 83C154 microcontrollers. The clear reading of the program contained in the ROM is made impossible due to an encryption through several random keys implemented during the manufacturing process ...
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... Electrical Characteristics Absolute Maximum Ratings* Ambiant Temperature Under Bias : C = commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I = industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . Voltage on VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . Voltage on Any Pin to VSS . . . . . . . . . . . . . . . –0 VCC + 0.5 V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Icc idle Freq 12 MHz Icc op = 1.3 Freq (MHz) + 4.5 mA Icc idle = 0.36 Freq (MHz) + 2.7 mA MATRA MHS Rev.F (14 Jan. 97) 80C154/83C154 * Notice Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only – +125 C and functional operation of the device at these or any other conditions – ...
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... Absolute Maximum Ratings* Ambient Temperature Under Bias : M = Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . Voltage on VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . Voltage on Any Pin to VSS . . . . . . . . . . . . . . . –0 VCC + 0.5 V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Freq > 12 MHz (Vcc = 5.5 V) Icc (mA) = 1.3 Freq (MHz) + 4.5 Icc Idle (mA) = 0.36 MATRA MHS Rev.F (14 Jan. 97) 80C154/83C154 * Notice Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only +70 C and functional operation of the device at these or any other conditions – ...
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... Note 1 : ICC is measured with all output pins disconnected ; XTAL1 driven TCHCL = 5 ns, VIL = VSS + .5 V, VIH = VCC –. XTAL2 N. RST = Port 0 = VCC. ICC would be slighty higher if a crystal oscillator used. Idle ICC is measured with all otput pins disconnected ; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 5 V, VIH = VCC -.5 V ...
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... PSEN to Address Valid TAVIV Address to Valid instr in TPLAZ PSEN low to Address Float External Program Memory Read Cycle MATRA MHS Rev.F (14 Jan. 97) 80C154/83C154 Example : TAVLL = Time for Address Valid to ALE low. TLLPL = Time for ALE low to PSEN low Output data READ signal Time Valid. ...
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... External Data Memory Characteristics SYMBOL PARAMETER TRLRH RD pulse Width TWLWH WR pulse Width TLLAX Address Hold After ALE TRLDV RD to Valid in TRHDX Data hold after RD TRHDZ Data float after RD TLLDV ALE to Valid Data In TAVDV Address to Valid Data IN TLLWL ALE ...
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... TXHDX Input Data Hold after Clock Rising Edge TXHDV Clock Rising Edge to Input Data Valid Shift Register Timing Waveforms MATRA MHS Rev.F (14 Jan. 97) 80C154/83C154 16 MHz 20 MHz 25 MHz MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX 750 600 480 563 ...
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... External Clock Drive Characteristics (XTAL1) SYMBOL PARAMETER FCLCL Oscillator Frequency TCLCL Oscillator period TCHCX High Time TCLCX Low Time TCLCH Rise Time TCHCL Fall Time External Clock Drive Waveforms AC Testing Input/Output Waveforms AC inputs during testing are driven at Vcc – 0.5 for a logic “1” and 0.45 V for a logic “0”. Timing measurements are made at VIH min for a logic “ ...
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... This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (T and WR propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. MATRA MHS Rev.F (14 Jan. 97) 80C154/83C154 www.DataSheet4U.com fully loaded ...
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... Ordering Information I 83C154C Part Number 83C154 Rom 80C154 External ROM 83C154C Secret ROM version 83C154T Secret Tag version Temperature Range blank : Commercial I : Industrial A : Automotive M : Military Package Type P: PDIL 40 S: PLCC 44 F1: PQFP 44 (Foot print 13.9 mm) F2: PQFP 44 (Foot print 12.3 mm) V: VQFP (1 ...