PDSP16540 Zarlink Semiconductor, PDSP16540 Datasheet - Page 5

• Manufacturer Part Number: PDSP16540
• Description: 32K BUCKET BUFFER
• Manufacturer: Zarlink Semiconductor

flow systems in which the transfer between system elements
is contolled by a continuously available system clock. This
system clock is usually at the maximum rate that the system
elements will allow, since it is governing the rate at which
processing can be performed on the acquired data. The rate
at which external data is actually inputed to the system ( the
sampling rate in DSP terminology ) is usually much slower
than the internal system, or computational, rate. The
PDSP16540 then provides a reservoir for data which is
FUNCTIONAL DESCRIPTION
N
M
L
K
J
H
G
F
E
D
C
B
A
The PDSP16540 is designed for use in synchronous data
GND
VDD
RS
D7
D6
D2
D0
WS
D4
IP
IP
IP
1
3
5
IP
6
1
WEN
RMF
DAV
D5
D3
D1
D8
IP
IP
IP
IP
0
2
4
7
2
D10
D9
IP
IP
8
9
3
Pin Out Diagram - Bottom View (84pin PGA - AC84)
D12
D11
11
IP
10
IP
4
D13
D14
13
IP
12
IP
5
VDD
VDD
D15
14
IP
6
D17
D16
16
15
IP
IP
acquired at the sampling rate and then processed with the
higher speed system clock rate.
strobe when a write enable input is active. The enbling signal
must meet the set up and hold times given in Table 1. Data is
read from the RAM using a read strobe which is expected to
be continuously availble and not to just go active when read
operations are actually needed. It is normally the high speed
system clock discussed earlier. All RAM addresses are
generated internally since the device is partitioning consecu-
7
Data is written to the RAM using an asynchronous write
GND
GND
D18
17
IP
8
D19
D20
19
IP
18
IP
9
D21
D22
21
20
IP
IP
10
D23
D24
22
23
IP
IP
11
MD2
MD3
MD5
MD0
D25
D28
D30
27
24
PDSP16540
IP
IP
31
29
IP
IP
12
GND
MD4
VDD
RES
MD1
D26
D27
D29
D31
26
IP
30
IP
28
25
IP
IP
13
3