PDSP16540 Zarlink Semiconductor, PDSP16540 Datasheet - Page 3

• Manufacturer Part Number: PDSP16540
• Description: 32K BUCKET BUFFER
• Manufacturer: Zarlink Semiconductor

The PDSP16540 Bucket Buffer is for use in systems which
require a reservoir in which a block of data is accumulated,
whilst previous data is being transferred to other system
elements and then processed. It thus prevents the loss of
incoming data whilst the previous block is being processed.
Like a FIFO all address are generated internally.
user to define both the length of the data block and also the
amount of the old data to be re-read before the new data is
added. The latter feature supports the block overlapping
requirements of Digital Signal Processing Systems perform-
ing Fast Fourier Transforms. It also provides wide, 32 bit, input
and output buses, unlike normal byte wide FIFO's. This wide
configuration supports the16 bit real and imaginary compo-
nents of the complex data found in many DSP systems.
PDSP16510 FFT Processor without any external logic. The
FFT Processor requires the support of an input buffer when
1024 point transforms are to be continuously performed and
no incoming data is to remain un-processed.
block, can be programmed in multiples of 32 up to a maximum
of 1024. The amount of new data in this block can separately
be programmed in multiples of 32 words. In this manner the
percentage of new data in a complete block is under the
control of the user, and the device is not restricted to only
supporting the requirements of the PDSP16510.
the loading of new data. This allows the next system compo-
nent to prepare itself to accept data. Data is not actually
transferred, however, until all the user defined amount of new
data has been loaded, and a Data Available Flag goes active.
The gap between the two flags can be programmed to provide
sufficient time to prepare the device which is to accept data
from the buffer. This provide a much more flexible solution
than the simple Full Flag offered by a standard FIFO.
PDSP16510 FFT Processor
PDSP16520 Quad Port Synchronous RAM
PDSP16116 Complex Multiplier
PDSP16318 Complex Accumulator
PDSP16330 Cartesian to Polar Converter
PDSP16340 Polar to Cartesian Converter
ASSOCIATED PRODUCTS
(Supersedes version in December 1993 Digital Video & Digital Signal Processing IC Handbook, HB3923-1)
It differs from a normal FIFO, however, by allowing the
In particular, the device can be directly connected to the
The number of words, which are read as a complete
A Read Me Flag is raised at a user defined point during
32K BUCKET BUFFER
PDSP16540
FEATURES
CONTROL
ENABLE
MODE
WRITE
32 BIT
DATA
I/P
read before new data is added
PDSP16510 FFT Processor when 1024 point
continuous transforms are performed
new data has been acquired
1K x 32 bit dual port RAM for use as a reservoir in
data flow systems
Up to 40 MHz read rates and 16 MHz write rates
Buffer size user programmable up to 1k words
A user programmble amount of old data can be re-
Provides the input buffer requirements for the
User programmable get ready to Read Me Flag
Data Available Flag indicates the required amount of
84 Pin PGA or 132 Pin QFP
WRITE STROBE
SYNC LOGIC
ADDRESS
Figure 1. Simplified Block Diagram
WRITE
WRITE
CONTROL LOGIC
1K X 32 BIT
DUAL PORT
RAM
ADVANCE INFORMATION
READ STROBE
ADDRESS
READ
READ
FEBRUARY 1995
PDSP16540
DS3715 - 2.1
RESET
AVAIL
32 BIT
READ
DATA
FLAG
FLAG
DATA
O/P
ME
1