PDSP16350 Mitel Networks Corporation, PDSP16350 Datasheet
PDSP16350
Related parts for PDSP16350
PDSP16350 Summary of contents
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... Supersedes version in December 1993 Digital Video & DSP IC Handbook, HB3923-1 The PDSP16350 provides an integrated solution to the need for very accurate, digitised, sine and cosine waveforms. Both these waveforms are produced simultaneously, with 16 bit amplitude accuracy, and are synthesised using a 34 bit phase accumulator ...
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... PDSP16350 N JUMP MODE DIN19 M DIN17 DIN18 L DIN15 DIN16 K DIN13 DIN14 J DIN11 DIN12 H GND DIN10 G DIN9 DIN8 F VDD DIN7 E DIN6 DIN5 D DIN4 DIN3 C DIN2 DIN1 B DIN0 COS15 A CLOCK GND COS14 DIN21 DIN23 VDD DIN26 DIN20 DIN22 DIN24 DIN25 COS13 COS11 ...
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... DIN21 90 DIN3 VDD 91 VDD DIN20 92 GND DIN19 93 DIN2 GND 94 DIN1 VDD 95 N/C DIN18 96 DIN0 MODE 97 N/C JUMP 98 CLK VDD 99 PDSP16350 GC SIG GND 100 101 VDD GND 102 103 N/C 104 COS15 COS14 105 106 N/C COS13 107 108 COS12 109 N/C COS11 110 111 N/C COS10 112 ...
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... PDSP16350 SIGNAL DESCRIPTION DIN33:0 Data bus for the input register. This input register provides a 34 bit, incremental or absolute, phase value, if the mode pin is low. Alternatively if the mode pin is high, it provides either an 18 bit phase increment value, via D17:0, and a 16 bit scale value via D33: bit phase increment value depending on the JUMP input see below ...
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... In a phase locked loop synthesiser N is large, in the PDSP16350 it is less than half. Log N is thus less than zero and phase noise improvement is obtained. The output waveforms are produced after a pipeline delay with respect to the DIN inputs ...
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... DIN33 0000 0001 1110 1000 0011 1001 1100 0111 The resolution would be 0.0006 Hz. It should be noted that the accuracy of the PDSP16350 cannot be any better than the accuracy of the incoming clock, and these resolutions are based on perfect incoming waveforms. ...
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... Such a quadrature heterodyning system, alternatively known splitter, is shown in Fig. 5. The output from an A/D converter drives the D33:18 inputs of the PDSP16350. If all sixteen inputs are not required, the unused least significant bits should be tied to ground, and the more significant inputs connected to the A/D converter. Multi- plying an input signal with a local oscillator in this manner produces both sum and difference components ...
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... PDSP16350 Modulated Frequency The output frequency can be modulated very simply, see Fig 8. Since the phase increment value can be loaded as a complete word every cycle, there is no need to provide internal double buffering to prevent spurious frequencies being gener- ated during the load operation. Binary Frequency Shift Keyed ...
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... The reset function is internally synchronised to the input clock Apply First Absolute Phase Data Jump Fig. 9 Phase Modulation Timing Diagram PDSP16350 First Result Absolute phase Available jump result ...
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... PDSP16350 ABSOLUTE MAXIMUM RATINGS (Note 1) Supply voltage Vcc Input voltage V IN Output voltage V OUT Clamp diode current per pin I (see note 2) K Static discharge voltage (HMB) Storage temperature T S Ambient temperature with power applied T Military Industrial Junction temperature Package power dissipation Thermal resistances Junction to Case ø ...
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... ORDERING INFORMATION Industrial (-40°C to +85°C) PDSP16350 / (20MHz - PGA) PDSP16350 / B0/ GC (20MHz - QFP) Military (-55°C to +125°C) PDSP16350 / (20MHz - PGA) PDSP16350 / A0/ GC (20MHz - QFP) PDSP16350 11 ...
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