MAS3587F Micronas, MAS3587F Datasheet - Page 37

• Manufacturer Part Number: MAS3587F
• Description: MPEG Layer 3 Audio Encoder/Decoder
• Manufacturer: Micronas

ADVANCE INFORMATION
Table 3–7: D0 Control Memory Cells
Micronas
Memory
Address
(hex)
D0:7f3
D0:7f4
D0:7f8
D0:7f9
D0:7fc
D0:7fd
D0:7fe
D0:7ff
1)
IEC 958 Amendment1, “Digital Audio Interface”
Function
Oscillator Frequency (reset = 18432
bit[19:0]
In order to achieve a correct internal operating frequency of the DSP, the nom-
inal crystal frequency has to be deposited into this memory cell.
Changes at this memory address must be validated by setting bit 0 of D0:7f1.
Output Clock Configuration (pin CLKO) (reset = 80000
bit[19]
The CLKO output pin of the MAS 3587F can be disabled via bit [19].
bit[18]
bit[17]
bit[16:9]
bit[8]
For a list of output frequencies at pin CLKO please refer to Table 2–1.
bit[7:0]
Changes at this memory address must be validated by setting bit[0] of D0:7f1.
S/PDIF
Soft Mute (reset = 0
bit[19:0]
Volume output control: left
Volume output control: left
Volume output control: right
Volume control: right
1)
channel status bits category code setting (reset = 8004
oscillator frequency in kHz
CLKO configuration
0
1 (reset)
Reserved, must be set to zero
Additional division by 2 if scaler is on (bit[8] cleared)
0 (reset)
1
Reserved, must be set to zero
Output clock scaler
0 (reset)
1
reserved, must be set to zero
0 (reset)
1
hex
)
output clock signal at CLKO
CLKO is tristate
oversampling factor 512/768
oversampling factor 256/384
set output clock according to audio sample rate
(see Table 2–1)
output clock fixed at 24.576 or 22.5792 MHz
mute off
mute on
right gain (reset = 80000
left gain (reset = 80000
right gain (reset = 0
left gain(reset = 0
dec
)
hex
hex
hex
)
)
hex
)
hex
)
)
Decoder
Decoder
Decoder
Decoder
Decoder
hex
) All
All
All
MAS 3587F
Name
OfreqControl
OutClkConfig
SpdOutBits
SoftMute
out_LL
out_LR
out_RL
out_RR
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