MAS3587F Micronas, MAS3587F Datasheet - Page 24

• Manufacturer Part Number: MAS3587F
• Description: MPEG Layer 3 Audio Encoder/Decoder
• Manufacturer: Micronas

MAS 3587F
3.3. DSP Core
The DSP Core of the MAS 3587F has two RAM banks
denoted D0 and D1. The word size is 20 bits. All RAM
addresses can be accessed in a 20-bit or a 16-bit
mode via I
states, the processor core also has an address space
of 256 data registers. All register and RAM addresses
are given in hexadecimal notation.
3.3.1. Access Protocol
The access of the DSP Core in the MAS 3587F uses a
special command syntax. The commands are exe-
cuted by the DSP during its normal operation without
any loss or interruption of the incoming data or outgo-
ing audio data stream. These I
controller accessing the internal DSP registers and
RAM cells and thus, monitoring internal states and set-
ting the parameters for the DSP firmware. This access
Fig. 3–2: General core access protocol
Table 3–4: Basic controller command codes
24
S
Code
(hex)
0...3
5
6
A
B
C
D
E
F
DW
Command
Run
Read Ancillary Data
Fast Program Download
Read from Register
Write to Register
Read D0 Memory
Read D1 Memory
Write D0 Memory
Write D1 Memory
2
C bus. For fast access of internal DSP
W
A
$68
W
2
C commands allow the
A
code , ...
Function
Start execution of an internal program. Run with start address 0 means
freeze the operating system.
The controller reads a block of MPEG Ancillary Data from the MAS 3587F
The controller downloads custom software via the PIO interface
The controller reads an internal register of the MAS 3587F
The controller writes an internal register of the MAS 3587F
The controller reads a block of the DSP memory
The controller reads a block of the DSP memory
The controller writes a block of the DSP memory
The controller writes a block of the DSP memory
A
... , ...
A
also provides a download option for alternative soft-
ware modules.
The MAS 3587F firmware scans the I
odically and checks for pending or new commands.
However, due to some time critical firmware parts, a
certain latency time for the response has to be
expected. The theoretical worst case response time
does not exceed 4 ms. However, the typical response
time is less than 0.5 ms.
Table 3–4 gives an overview over the different com-
mands which the DSP Core receives via the I
register. The “Code” is always the first data nibble
transmitted after the “data_write” subaddress byte. A
second auxiliary code nibble is used for the short
memory (16-bit) access commands.
Due to the 16-bit width of the I
actions transmit telegrams with multiples of 16 data
bits.
... , ...
ADVANCE INFORMATION
2
C data register, all
2
C interface peri-
Micronas
2
C data