USB2503-HZH Standard Microsystems Corp., USB2503-HZH Datasheet - Page 12

• Manufacturer Part Number: USB2503-HZH
• Description: Interface, Integrated USB2.0 Compatible 3-Port Hub
• Manufacturer: Standard Microsystems Corp.

Revision 1.3 (08-24-04)
Crystal Output
Input/External
RESET Input
Internal 1.8V
VDDPLL1P8
Self-Power /
Analog Test
Clock Input
Clock Input
Bus-Power
TEST Pins
regulator
VDD1P8
voltage
Crystal
Enable
NAME
enable
NAME
Detect
&
VDDA18PLL
SELF_PWR
CLKIN_EN
RESET_N
TEST[1:0]
SYMBOL
SYMBOL
REG_EN
ATEST/
XTAL1/
VDD18
CLKIN
XTAL2
Table 4.4 Power, Ground, and No Connect
Table 4.3 Miscellaneous Pins
OCLKx
ICLKx
TYPE
TYPE
AIO
IPD
IS
I
I
7
24MHz crystal or external clock input.
This pin connects to either one terminal of the crystal or
to an external 24MHz clock when a crystal is not used.
24MHz Crystal
This is the other terminal of the crystal, or left
unconnected when an external clock source is used to
drive XTAL1/CLKIN. It must not be used to drive any
external circuitry other than the crystal circuit.
Clock In Enable:
Low = XTAL1 and XTAL2 pins configured for use with
external crystal
High = XTAL1 pin configured as CLKIN, and must be
driven by an external CMOS clock.
This active low signal is used by the system to reset the
chip. The minimum active low pulse is 100ns.
Detects availability of local self-power source.
Low = Self/local power source is NOT available (i.e., 7-
Port Hub gets all power from Upstream USB VBus).
High = Self/local power source is available.
Used for testing the chip. User must treat as a no-
connect or connect to ground. For board testing, all
signal pins are included in an XNOR chain, Please see
Chapter 6, "XNOR Test," on page 31
the configuration and use of the XNOR mode.
This signal is used for testing the analog section of the
chip, and to enable or disable the internal 1.8v regulator.
This pin must be connected to VDDA3P3 to enable the
internal 1.8V regulator, or to VSS to disable the internal
regulator.
When the internal regulator is enabled, the 1.8V power
pins must be left unconnected, except for the required
bypass capacitors.When the PHY is in test mode, the
internal regulator is disabled and the ATEST pin
functions as a test pin.
+1.8V core power.
If the internal regulator is enabled, then VDD18 pin
closest to VDD33CR must have a 4.7
±20% (ESR <0.1
+1.8V Filtered analog power for internal PLL.
If the internal regulator is enabled, then this pin must
have a 4.7
to VSS
µ
F (or greater) ±20% (ESR <0.1
Ω)
Integrated USB2.0 Compatible 3-Port Hub
capacitor to VSS
FUNCTION
FUNCTION
for more details on
µ
F (or greater)
Ω)
SMSC USB2503
capacitor
Datasheet