HT45R34 Holtek Semiconductor, HT45R34 Datasheet - Page 9

• Manufacturer Part Number: HT45R34
• Description: C/R to F Type 8-Bit OTP MCU
• Manufacturer: Holtek Semiconductor

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abled, the stack is not full, and the external interrupt is
active, a subroutine call to location 04H or 08H will
occur. The interrupt request flags, EIF0 or EIF1, and the
EMI bit will all be cleared to disable other interrupts.
The internal Timer/Event Counter interrupt is initialised
by setting the Timer/Event Counter interrupt request
flag, TF; bit 6 in INTC0. A timer interrupt will be gener-
ated when the timer overflows. After the interrupt is en-
abled, and the stack is not full, and the TF bit is set, a
subroutine call to location 0CH will occur. The related
interrupt request flag, TF, is reset, and the EMI bit is
cleared to disable other interrupts.
The external RC oscillation converter interrupt is initial-
ized by setting the external RC oscillation converter in-
terrupt request flag, RCOCF; bit 4 of INTC1. This is
caused by a Timer A or Timer B overflow. When the in-
terrupt is enabled, and the stack is not full and the
RCOCF bit is set, a subroutine call to location 10H will
occur. The related interrupt request flag, RCOCF, will be
reset and the EMI bit cleared to disable further inter-
rupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are held until the RETI in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1, if the stack is not full. To
return from the interrupt subroutine, a RET or RETI
instruction may be invoked. RETI will set the EMI bit to
enable an interrupt service, but RET will not.
Rev. 1.20
1~3, 5~7
Bit No.
Bit No.
0
1
2
3
4
5
6
7
0
4
ERCOCI Controls the external RC oscillation converter interrupt (1= enabled; 0= disabled)
RCOCF External RC oscillation converter request flag (1= active; 0= inactive)
Label
Label
EEI0
EEI1
EIF0
EIF1
EMI
ETI
TF
Controls the master (global) interrupt (1= enabled; 0= disabled)
Controls the external interrupt 0 (1= enabled; 0= disabled)
Controls the external interrupt 1 (1= enabled; 0= disabled)
Controls the Timer/Event Counter interrupt (1= enabled; 0= disabled)
External interrupt 0 request flag (1= active; 0= inactive)
External interrupt 1 request flag (1= active; 0= inactive)
Internal Timer/Event Counter request flag (1= active; 0= inactive)
Unused bit, read as 0
Unused bit, read as 0
INTC0 (0BH) Register
INTC1 (1EH) Register
9
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
The EMI, EEI0, EEI1, ETI and ERCOCI bits are all used
to control the enable/disable status of interrupts. These
bits prevent the requested interrupt from being serviced.
Once the interrupt request flags, TF, RCOCF, EIF1 and
EIF0, are all set, they remain in the INTC1 or INTC0 reg-
isters respectively until the interrupts are serviced or
cleared by a software instruction.
It is recommended that a program does not use the
rupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only one
stack is left and enabling the interrupt is not well con-
trolled, the original control sequence may be damaged
once the CALL is executed in the interrupt subroutine.
External Interrupt 0
External Interrupt 1
Timer/Event Counter Overflow
External RC Oscillation
Converter Interrupt
CALL subroutine within the interrupt subroutine. Inter-
Function
Function
Interrupt Source
Interrupt Priority
Priority
October 15, 2007
1
2
3
4
HT45R34
Vector
0CH
04H
08H
10H