HT45R34 Holtek Semiconductor, HT45R34 Datasheet - Page 8

• Manufacturer Part Number: HT45R34
• Description: C/R to F Type 8-Bit OTP MCU
• Manufacturer: Holtek Semiconductor

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Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic opera-
tions. The ALU provides the following functions:
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register - STATUS
This 8-bit register contains the zero flag (Z), carry flag
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO). It
also records the status information and controls the op-
eration sequence.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition opera-
tions related to the status register may give different re-
sults from those intended. The TO flag can be affected
only by a system power-up, a WDT time-out or execut-
ing the CLR WDT or HALT instruction.
The PDF flag can be affected only by executing a
power-up.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or exe-
cuting the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can cor-
rupt the status register, precautions must be taken to
save it properly.
Rev. 1.20
HALT
Arithmetic operations
Logic operations
Rotation
Increment and Decrement
Branch decision
Bit No.
6~7
0
1
2
3
4
5
or
RL, RR, RLC, RRC
Label
CLR WDT
PDF
OV
AC
TO
C
Z
SZ, SNZ, SIZ, SDZ ....
AND, OR, XOR, CPL
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
PDF is cleared by system power-up or executing the CLR WDT instruction.
PDF is set by executing the HALT instruction.
TO is cleared by system power-up or executing the CLR WDT or HALT instruction.
TO is set by a WDT time-out.
Unused bit, read as 0
ADD, ADC, SUB, SBC, DAA
instruction or a system
INC, DEC
Status (0AH) Register
8
Interrupt
The devices provides two external interrupts, one inter-
nal 8-bit timer/event counter interrupt and one external
RC oscillation converter interrupt. The interrupt control
register 0, INTC0, and interrupt control register 1,
INTC1, both contain the interrupt control bits that are
used to set the enable/disable and interrupt request
flags.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked, as the EMI bit will be cleared au-
tomatically. However this scheme may prevent further
interrupt nesting. Other interrupt requests may happen
during this interval but only the interrupt request flag is
recorded. If a certain interrupt requires servicing within
the service routine, the EMI bit and the corresponding
bit of the INTC0 and INTC1 registers may be set to allow
interrupt nesting.
If the stack is full, the interrupt request will not be ac-
knowledged, even if the related interrupt is enabled, un-
til the Stack Pointer is decremented. If immediate
service is desired, the stack must be prevented from be-
coming full.
All interrupts have a wake-up capability. As an interrupt
is serviced, a control transfer occurs by pushing the pro-
gram counter onto the stack, followed by a branch to a
subroutine at a specified location in the program mem-
ory. Only the program counter is pushed onto the stack.
If the contents of the accumulator or status register are
altered by the interrupt service program, this may cor-
rupt the desired control sequence, therefore their con-
tents should be saved in advance.
External interrupts are triggered by an edge transition
on pins INT0 or INT1. A configuration option enables
these pins as interrupts and selects if they are active on
high to low or low to high transitions. If active their re-
lated interrupt request flag, EIF0; bit 4 in INTC0, and
EIF1; bit 5 in INTC0, will be set. After the interrupt is en-
Function
October 15, 2007
HT45R34