HD1-6408-9 Intersil Corporation, HD1-6408-9 Datasheet - Page 4

• Manufacturer Part Number: HD1-6408-9
• Description: CMOS Asynchronous Serial Manchester Adapter (ASMA)
• Manufacturer: Intersil Corporation

Encoder Operation
The Encoder requires a single clock with a frequency of
twice the desired data rate applied at the SClock input. An
auxiliary divide by six counter is provided on chip which can
be utilized to produce the SClock by dividing the DClock.
The Encoder’s cycle begins when EE is high during a falling
edge of ESC (1). This cycle lasts for one word length or
twenty ESC periods. At the next low-to-high transition of the
ESC, a high at SS input actuates a Command sync or a low
will produce a Data sync for that word (2). When the Encoder
is ready to accept data, the SD output will go high and
remain high for sixteen ESC periods (3) - (4).
TIMING
BOO
BZO
ESC
SCI
SDI
SD
EE
SS
1
VALID
2
1ST HALF
SYNC
0
1
2ND HALF
SYNC
3
2
15
DON’T CARE
15
15
DON’T CARE
3
14
14
14
4
13
13
13
5
HD-6408
12
5-4
12
12
6
During these sixteen periods the data should be clocked into
the SD Input with every high-to-low transition of the ESC (3)
- (4). After the sync and Manchester II encoded data are
transmitted through the BOO and BZO outputs, the Encoder
adds on an additional bit which is the (odd) parity for that
word (5). If ENCODER ENABLE is held high continuously,
consecutive words will be encoded without an interframe
gap. ENCODER ENABLE must go low by time (5) as shown
to prevent a consecutive word from being encoded. At any
time a low on OI will force both bipolar outputs to a high state
but will not affect the Encoder in any other way.
To Abort the Encoder transmission a positive pulse must be
applied at MR. Any time after or during this pulse, a low-to-
high transition on SCI clears the internal counters and initial-
izes the Encoder for a new word.
11
11
11
7
10
3
15
3
3
2
16
2
2
1
17
1
1
0
18
0
0
4
5
19
P
P