HD1-6402R-9 Intersil Corporation, HD1-6402R-9 Datasheet
HD1-6402R-9
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HD1-6402R-9 Summary of contents
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... SAJI IV CMOS process permits operation clock frequencies up to 8.0MHz (500K Baud). Power requirements, by compar- ison, are reduced from 300mW to 10mW. Status logic increases flexibility and simplifies the user interface. 2MHz = 125K BAUD o C HD3-6402R HD1-6402R 5962-9052501MQA HD-6402 (PDIP, CERDIP) TOP VIEW ...
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Functional Diagram (24) TRE (22) TBRE † (23) TBRL TRANSMITTER TIMING AND (40) TRC CONTROL (38) CLS1 (37) CLS2 (34) CRL (21) MR (17) RRC RECEIVER TIMING AND CONTROL (18) DRR (19) DR † (16) SFD † THESE OUTPUTS ARE ...
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Pin Description PIN TYPE SYMBOL DESCRIPTION 1 V † Positive Voltage Supply Connection 3 GND Ground 4 I RRD A high level on RECEIVER REGISTER DISABLE forces the receiver holding out-puts RBR1-RBR8 to high impedance state. ...
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Transmitter Operation The transmitter section accepts parallel data, formats the data and transmits the data in serial form on the Transmitter Regis- ter Output (TRO) terminal (See serial data format). Data is loaded from the inputs TBR1-TBR8 into the Transmitter ...
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Start Bit Detection The receiver uses a 16X clock timing. The start bit could have occurred as much as one clock cycle before it was detected, as indicated by the shaded portion (A). The center of the start bit is ...
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Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...