HD1-6402B-9 Intersil Corporation, HD1-6402B-9 Datasheet - Page 5

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HD1-6402B-9

Manufacturer Part Number
HD1-6402B-9
Description
CMOS Universal Asynchronous Receiver Transmitter (UART)
Manufacturer
Intersil Corporation
Datasheet

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Start Bit Detection
The receiver uses a 16X clock timing. The start bit could have
occurred as much as one clock cycle before it was detected,
as indicated by the shaded portion (A). The center of the start
bit is defined as clock count 7 1/2. If the receiver clock is a
Interfacing with the HD-6402
SYSTEM
DIGITAL
RRI INPUT
TBR1
TBR8
CONTROL
CONTROL
RB1
RB8
TRANSMITTER
CLOCK
RECEIVER
HD-6402
START BIT
TRO
RRI
A
FIGURE 5. TYPICAL SERIAL DATA LINK
RECEIVER
FIGURE 3. SERIAL DATA FORMAT
LSB
DRIVER
RS232
RS232
81/2 CLOCK CYCLES
71/2 CLOCK CYCLES
HD-6402
FIGURE 4.
START
5-8 DATA BITS
5
symmetrical square wave, the center of the start bit will be
located within ±1/2 clock cycle, ±1/32 bit or 3.125% giving a
receiver margin of 46.875%. The receiver begins searching
for the next start bit at the center of the first stop bit.
RECEIVER
DRIVER
RS232
RS232
MSB
1, 11/2 OR 2 STOP BITS
COUNT 71/2 DEFINED
CENTER OF START BIT
RRI
TRO
TRANSMITTER
RECEIVER
HD-6402
CONTROL
CONTROL
PARITY
TBR1
TBR8
RB1
RB8
IF ENABLED
SYSTEM
DIGITAL

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