LMX3305 National Semiconductor, LMX3305 Datasheet - Page 18

• Manufacturer Part Number: LMX3305
• Description: Triple Phase Locked Loop for RF Personal Communications
• Manufacturer: National Semiconductor

www.national.com
Divide ratio for RF R counter is from 2 to 255.
2.0 Programming Description
2.5.1 8-Bit RF Programming Reference Divider Ratio (RF R Counter)
2.5.2 FSTL_CNTR (RF_R[20]-[14])
The Fastlock Timeout Counter is a 10 bit counter wherein only the seven MSB bits are programmable. (The number of phase de-
tector cycles the fastlock mode remains in HIGH gain is the binary FSTL_CNTR value loaded multiplied by eight.)
2.5.3 FSTM (RF_R[13]-[12]) and FSTSW (RF_R[11]-[10])
Fastlock enables the designer to achieve both fast frequency transitions and good phase noise performance by dynamically
changing the PLL loop bandwidth. The Fastlock modes allow wide band PLL fast locking with seamless transition to a low phase
noise narrow band PLL. Consistent gain and phase margins are maintained by simultaneously changing charge pump current
magnitude and loop filter damping resistor. In the LMX3305, the RF fastlock can achieve substantial improvement in lock time by
increasing the charge pump current by 4X, 7X or 9X, which causes a 2X, 2.6X or 3X increase in the loop bandwidth respectively.
The damping resistors are connected to FSTSW pins.
When bit FSTM2 and/or FSTM1 is set HIGH, the RF fastlock is enabled. As a new frequency is loaded, RF_Sw2 pin and/or
RF_Sw1 pin goes to a LOW state to switch in the damping resistors, the RF CP
counter starts counting. Once the timeout counter finishes counting, the PLL returns to its normal operation (the Icpo gain is
forced to 100 µA irrespective of RF_Icpo bits).
When bit FSTM2 and/or FSTM1 is set LOW, pins RF_Sw2 and/or RF_Sw1 can be toggled HIGH or LOW to drive other devices.
RF_Sw2 and/or RF_Sw1 can also be set LOW to switch in different damping resistors to change the loop filter performance.
FSTSW bits control the output states of the RF_Sw2 and RF_Sw1 pins.
2.5.4 FRAC_CAL (RF_R[9]-[5])
These five bits allow the users to optimize the fractional circuitry, therefore reducing the fractional reference spurs. The MSB bit,
RF_R[9], activates the other four calibration bits RF_R[8]-[5]. These four bits can be adjusted to improve fractional spur. Improve-
ments can be made by selecting the bits to be one greater or less than the denominator value. For example, in the 1/16 fractional
mode, these four bits can be programmed to 15 or 17. In normal operation, these bits should be set to zero.
RF_R[12] FSTM1
RF_R[13] FSTM2
Divide Ratio
Phase Detect Cycles
255
2
3
•
0
0
1
0
0
1
1008
1016
24
32
•
0
0
1
•
RF_R[10] FSTSW1
RF_R[11] FSTSW2
0
0
1
1
•
0
1
x
0
1
x
0
0
1
•
(Continued)
0
0
1
1
•
0
0
1
•
18
RF_Sw1 pin reflects RF_SwBit “0” logic state
RF_Sw1 pin reflects RF_SwBit “1” logic state
RF_Sw1 pin LOW while T.O. counter is active
RF_Sw2 pin reflects RF_SwBit “0” logic state
RF_Sw2 pin reflects RF_SwBit “1” logic state
RF_Sw2 pin LOW while T.O. counter is active
0
0
1
1
•
RF_R_CNTR [7:0]
0
0
1
•
FSTL_CNTR [6:0]
0
0
1
1
•
RF_Sw1 Output Function
RF_Sw2 Output Function
o
0
0
1
•
is set to a higher gain, and fastlock timeout
0
1
1
1
•
0
0
1
•
1
0
1
1
•
1
1
1
•
1
0
0
1
•
0
1
1
•