CY7C4271-15AC Cypress Semiconductor Corp, CY7C4271-15AC Datasheet
CY7C4271-15AC
Specifications of CY7C4271-15AC
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CY7C4271-15AC Summary of contents
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... Center power and ground pins for reduced noise ■ Supports free running 50% duty cycle clock inputs ■ Width Expansion Capability ■ Military temp SMD Offering – CY7C4271-15LMB ■ 32-pin PLCC/LCC and 32-pin TQFP ■ Pin compatible density upgrade to CY7C42X1 family ■ ...
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Logic Block Diagram WCLK WEN1 WRITE CONTROL WRITE POINTER RESET RS LOGIC Document #: 38-06015 Rev 0–8 INPUT REGISTER WEN2/ LD RAM ARRAY 16K x 9 32K x 9 THREE-STATE OUTPUT REGISTER OE Q 0–8 RCLK CY7C4261, CY7C4261 ...
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... HIGH, the FIFO’s outputs are in High Z (high impedance) state. Document #: 38-06015 Rev. *D Figure 2. Pin Diagram - 32-Pin TQFP (Top View WEN1 D 0 WCLK PAF LD WEN2/ PAE V CC GND REN1 7 Q RCLK REN2 Description CY7C4261, CY7C4261 WEN1 2 23 WCLK 3 WEN2/LD 22 CY7C4261 CY7C4271 Page [+] Feedback ...
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Functional Description The CY7C4261/71 provides four status pins: Empty, Full, Programmable Almost Empty, and Programmable Almost Full. The Almost Empty/Almost Full flags are programmable to single word granularity. The programmable flags default to Empty + 7 and Full – 7. ...
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... PAF. PAE is synchronized to the LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW when the number of unread words in the FIFO is greater than or equal to CY7C4261 (16K-m) and CY7C4271 (32K-m). PAF is set HIGH by the LOW-to-HIGH transition of WCLK when the number of available memory locations is greater than m. ...
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Figure 4. Block Diagram of 16K × 18/32K × 18 Deep Sync FIFO Memory Used in a Width Expansion Configuration DATAIN ( WRITECLOCK (WCLK) WRITE ENABLE 1(WEN1) WRITE ENABLE 2/LOAD (WEN2/LD) PROGRAMMABLE(PAF) FULL FLAG (FF FULL ...
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Maximum Ratings [4] Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature .......................................−65 Ambient Temperature with Power Applied....................................................−55 Supply Voltage to Ground Potential .................−0.5V to +7.0V DC Voltage Applied to ...
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OUTPUT C INCLUDING L JIG AND SCOPE Equivalent to: THÉVENIN EQUIVALENT 420Ω OUTPUT Switching Characteristics Over the Operating Range Parameter Description t Clock Cycle Frequency S t Data Access Time A t Clock Cycle Time CLK t Clock HIGH ...
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Switching Waveforms WCLK D – WEN1 WEN2 (if applicable SKEW1 RCLK REN1, REN2 RCLK t ENS REN1, REN2 EF Q – OLZ OE WCLK WEN1 WEN2 Notes 14 the minimum time ...
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Switching Waveforms (continued) RS REN1, REN2 WEN1 [18] WEN2/LD EF,PAE FF,PAF Figure 9. First Data Word Latency after Reset with Read and Write WCLK –D D (FIRST VALID WRITE ...
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Switching Waveforms (continued) WCLK –D DATA WRITE ENH ENS WEN1 t t ENS ENH WEN2 (if applicable) t FRL RCLK t SKEW1 EF REN1, REN2 LOW OE DATA IN OUTPUT REGISTER Q ...
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... If a write is performed on this rising edge of the write clock, there are Full − (m−1) words of the FIFO when PAF goes LOW. 25. PAF offset = m. 26. 16,384 − m words for CY7C4261, 32,768 − m words for CY7C4271. 27 the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of ...
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Switching Waveforms (continued) t CLK t CLKH WCLK t ENS WEN2/LD t ENS WEN1 – PAE OFFSET t CLK t CLKH RCLK t ENS WEN2/LD t ENS REN1, REN2 Q – Document #: ...
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NORMALIZED t VOLTAGE 1.20 1.10 1.00 0.90 0.80 4.00 SUPPLY VOLTAGE (V) NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.40 1.20 1. 3. 25° MHz 0.60 4.00 4.50 5.00 5.50 6.00 ...
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... CY7C4261-25JC 25 CY7C4261-25AI CY7C4261-25JI CY7C4261-35AC CY7C4261-35JC 35 CY7C4261-35AI CY7C4261-35JI 32Kx9 Deep Sync FIFO Speed (ns) Ordering Code Package Diagram 10 CY7C4271-10AC CY7C4271-10JC CY7C4271-10AI CY7C4271-10JI 15 CY7C4271-15AC CY7C4271-15AXC CY7C4271-15JC CY7C4271-15AI CY7C4271-15JI CY7C4271-15LMB 5962-9736101QYA 25 CY7C4271-25AC CY7C4271-25JC CY7C4271-25AI CY7C4271-25JI 35 CY7C4271-35AC CY7C4271-35JC CY7C4271-35AI CY7C4271-35JI Document #: 38-06015 Rev. *D Package Type 51-85063 32-Pin Thin Quad Flat Pack ( ...
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Table 4. DC Characteristics Parameters Max ...
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Package Diagrams Figure 17. 32-Pin Thin Plastic Quad Flatpack (7 × 7 × 1.0 mm) Document #: 38-06015 Rev. *D Figure 18. 32-Pin Plastic Leaded Chip Carrier CY7C4261, CY7C4261 51-85063 *B 51-85002 *B Page [+] Feedback ...
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Package Diagrams (continued) Figure 19. 32-Pin Rectangular Leadless Chip Carrier Document #: 38-06015 Rev. *D CY7C4261, CY7C4261 MIL-STD-1835 C-12 51-80068-** Page [+] Feedback ...
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... Document History Page Document Title: CY7C4261/CY7C4271, 16K/32K x 9 Deep Sync FIFOs Document Number: 38-06015 Orig. of Submission REV. ECN Change ** 106476 SZV *A 122267 RBI *B 127853 FSG *C 393437 ESH *D 2556036 VKN/AESA Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress ...