MC56F8367 Freescale Semiconductor, MC56F8367 Datasheet - Page 149
MC56F8367
Manufacturer Part Number
MC56F8367
Description
(MC56F8167 / MC56F8367) 16-bit Digital Signal Controllers
Manufacturer
Freescale Semiconductor
Datasheet
1.MC56F8367.pdf
(184 pages)
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DCAOE and DCAEO are calculated as follows:
The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some parameters
contain two sets of numbers to account for this difference. Use the “Wait States Configuration” column
of
Note:
Freescale Semiconductor
Preliminary
Table 10-16
A0-Axx,CS
D0-D15
DCAOE =
DCAEO =
WR
RD
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
When multiple lines are given for the same wait state configuration, calculate each and then select the
smallest or most negative.
to make the appropriate selection.
=
=
Example of DCAOE and DCAEO calculation:
Assuming prescaler is set for ÷ 1 and prescaler clock is selected by ZSRC, if XTAL duty cycle
ranges between 45% and 60% high;
DCAOE = .50 - .60 = - 0.1
DCAEO = .45 - .50 = - 0.05
0.5 - MAX XTAL duty cycle, if ZSRC selects prescaler clock and the prescaler is set to ÷ 1
0.0 all other cases
MIN XTAL duty cycle - 0.5, if ZSRC selects prescaler clock and the prescaler is set to ÷ 1
0.0 all other cases
t
Figure 10-4 External Memory Interface Timing
WRWR
t
AWR
t
DWR
t
Data Out
DOS
56F8367 Technical Data, Rev. 7.0
t
WR
t
t
DOH
WAC
t
WRRD
t
ARDA
t
AD
t
ARDD
t
RDD
t
RD
Data In
External Memory Interface Timing
t
DRD
t
RDA
t
RDRD
t
RDWR
149