MC56F8367 Freescale Semiconductor, MC56F8367 Datasheet - Page 128

• Manufacturer Part Number: MC56F8367
• Description: (MC56F8167 / MC56F8367) 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor

6.7 Power Down Modes Overview
The 56F8367/56F8167 operate in one of three power-down modes as shown in
All peripherals, except the COP/watchdog timer, run off the IPBus clock frequency, which is the same as
the main processor frequency in this architecture. The maximum frequency of operation is
SYS_CLK = 60MHz.
Refer to the PCE register in
frequency which can be controlled through the OCCS.
6.8 Stop and Wait Mode Disable Function
128
Run
Wait
Stop
Mode
Permanent
Disable
Clock
Select
Reprogrammable
Disable
Active
Core and memory
clocks disabled
System clocks continue to be generated in
the SIM, but most are gated prior to
reaching memory, core and peripherals.
Core Clocks
Table 6-4 Clock Operation in Power Down Modes
Part 6.5.9
Figure 6-17 Stop Disable Circuit
Active
Active
Peripheral Clocks
Reset
56F8367 Technical Data, Rev. 7.0
and ADC power modes. Power is a function of the system
D
D-FLOP
C
D
D-FLOP
C
R
Device is fully functional
Peripherals are active and can produce interrupts if they
have not been masked off.
Interrupts will cause the core to come out of its
suspended state and resume normal operation.
Typically used for power-conscious applications.
The only possible recoveries from Stop mode are:
1. CAN traffic (1st message will be lost)
2. Non-clocked interrupts
3. COP reset
4. External reset
5. Power-on reset
Q
Q
Note: Wait disable circuit is similar
Description
STOP_DIS
56800E
Table 6-3
Freescale Semiconductor
.
Preliminary