CY8CPLC10 Cypress Semiconductor, CY8CPLC10 Datasheet - Page 8

• Manufacturer Part Number: CY8CPLC10
• Description: Powerline Communication Solution
• Manufacturer: Cypress Semiconductor

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Table 4. Memory Field Description (continued)
Document Number: 001-50001 Rev. *D
TX_Gain
CMP
PGA
New_RX_Msg
RX_DA_Type
RX_SA_Type
RX_Msg_Length
8-bit Logical Address
16-bit Logical Address
64-bit Physical Address
Field Name
Note: This register is cleared when the user sets INT_Clear to Logic 0
4
3
3
1
1
1
5
No. of Bits
RX_Message_INFO Register (0x40)
RX_SA Register (0x41 - 0x48)
INT_Status Register (0x69)
RX_Gain Register (0x33)
0000 - 0.008
0001 - 0.012
0010 - 0.020
0011 - 0.027
0100 - 0.039
0101 - 0.055
0110 - 0.078
0111 - 0.109
1000 - 0.156
1001 - 0.219
1010 - 0.313
1011 - 0.375
1100 - 0.500
1101 - 0.711
1110 - 1.000
000 - 0.021
001 - 0.042
010 - 0.062
011 - 0.125
100 - 0.250
101 - 0.375
110 - 0.500
111 - 0.625
001 - 1.0
010 - 2.0
011 - 4.0
100 - 8.0
101 - 16.0
110 - 24.0
111 - 48.0
1 - New Packet received
Note: User sets this bit to Logic 0 after reading the RX
Message. This allows the device to receive a new RX
message
1 - Group Addressing
0 - Logical Address
1 - Physical Address
5-bit value for variable payload length. The payload
length can vary from 0 to 31.
0x41
0x41 - LSB
0x42 - MSB
0x41 - MSB
|
0x48 - LSB
000 - 1.0
0 - No Packet received
0 - Logical / Physical Addressing
Description
CY8CPLC10
Page 8 of 25
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