MC33886 Motorola, MC33886 Datasheet - Page 7

• Manufacturer Part Number: MC33886
• Description: 5.0 A H BRIDGE
• Manufacturer: Motorola

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 5.0 V
reflect the approximate parameter mean at T
TIMING CHARACTERISTICS
Notes
PWM Frequency (Note 20)
Maximum Switching Frequency During Active Current Limiting (Note 21)
Output ON Delay (Note 22)
Output OFF Delay (Note 22)
Output Rise and Fall Time (Note 23)
Output Latch-OFF Time
Output Blanking Time
Output FET Body Diode Reverse Recovery Time (Note 24)
Disable Delay Time (Note 25)
Short Circuit/Overtemperature Turn-
Power-OFF Delay Time
20.
21.
22.
23.
24.
25.
26.
V+ = 14 V
V+ = 14 V
V+ = 14 V, I
The outputs can be PWM controlled from an external source. This is typically done by holding one input high while applying a PWM pulse
train to the other input. The maximum PWM frequency obtainable is a compromise between switching losses and switching frequency. Refer
to Typical Switching Waveforms,
The Maximum Switching Frequency during active current limiting is internally implemented. The internal control produces a constant OFF-
time PWM of the output. The output load current effects the Maximum Switching Frequency.
Output Delay is the time duration from the midpoint of the IN1 or IN2 input signal to the 10% or 90% point (dependent on the transition
direction) of the OUT1 or OUT2 signal. If the output is transitioning High-to-Low, the delay is from the midpoint of the input signal to the 90%
point of the output response signal. If the output is transitioning Low-to-High, the delay is from the midpoint of the input signal to the 10%
point of the output response signal. See
Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal. See
Parameter is guaranteed by design but not production tested.
Disable Delay Time is the time duration from the midpoint of the D (disable) input signal to 10% of the output tri-state response. See
page 8.
Increasing currents will become limited at I
latch-OFF. See
will cause the active current limiting to progressively "fold back" (or decrease) to 2.5 A typical at 175
See
Figure
OUT
5, page 8.
= 3.0 A
Figures 6
Characteristic
and 7, page 9. Active current limiting will cause junction temperatures to rise. A junction temperature above 160
OFF
Freescale Semiconductor, Inc.
Figures 11
Time (Note 26)
For More Information On This Product,
Figure
LIM
A
≤
through 18, pp. 12–13.
= 25°C under nominal conditions unless otherwise noted.
V+
. Hard shorts will breach the I
Go to: www.freescale.com
2, page 8.
≤
28 V and -40°C
≤
T
A
≤
SCH
125°C unless otherwise noted. Typical values noted
t
Symbol
d(disable)
t
t
t
f
d(OFF)
FAULT
f
d
t
t
or I
PWM
MAX
f
t
pod
(ON)
t
t
, t
rr
a
b
SCL
r
limit, forcing the output into an immediate tri-state
Min
100
2.0
15
12
–
–
–
–
–
–
–
°
C where thermal latch-OFF will occur.
20.5
16.5
Typ
5.0
4.0
1.0
–
–
–
–
–
–
Figure
Max
8.0
8.0
5.0
10
20
18
18
26
21
–
–
4, page 8.
Figure
Unit
33886
kHz
kHz
ms
µs
µs
µs
µs
µs
ns
µs
µs
°
3,
C
7