NCP5220 ON Semiconductor, NCP5220 Datasheet
NCP5220
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NCP5220 Summary of contents
Page 1
... NCP5220 3−in−1 PWM Dual Buck and Linear Power Controller The NCP5220 3−in−1 PWM a Dual Buck and Linear Power Controller complete power solution for MCH and DDR memory. This IC combines the efficiency of PWM controllers for the VDDQ supply and the MCH core supply voltage with the simplicity of linear regulator for the VTT termination voltage ...
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... CPM1 RZM2 RZM1 5VDUAL R6 TG_1P5 M3 VMCH L 1 BG_1P5 COUT3 M4 NCP5220 BOOT SS 5VDUAL VTT TG_DDQ FBVTT AGND SW_DDQ NCP5220 BG_DDQ PGND FB1P5 COMP FBDDQ VDDQ PGND Figure 1. Application Diagram http://onsemi.com Zener 5VDUAL M1 VDDQ 2 COUT1 M2 CZ1 CZ2 ...
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... BOOT_ R10 UVLO VREF R11 5VDUAL R12 5VDUAL_ UVLO VREF R13 _5VDLGD SS OSC S0 CSS S3 1805 Phase Shift S0 VTT Regulation Control AGND NCP5220 THERMAL SHUTDOWN TSD S0 CONTROL S3 LOGIC VOCP + ILIM + − VCC VDDQ and V1P5 PGND PWM VCC LOGIC PGND AMP A1 VCC ...
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... This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) " 2.0 kV per JEDEC standard: JESD22–A114. Machine Model (MM) " 200 V per JEDEC standard: JESD22–A115. 2. Latchup Current Maximum Rating: " 150 mA per JEDEC standard: JESD78. NCP5220 Description Symbol ...
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... Minimum Duty Cycle Maximum Duty Cycle Soft−Start Pin Current for DDQ DDQ ERROR AMPLIFIER DC Gain Gain−Bandwidth Product Slew Rate 3. Guaranteed by design, not tested in production. NCP5220 = 0°C to 70° 1.7 mH, COUT1 = 3770 mF, A Symbol Test Conditions V5VDUAL VBOOT I5VDL_S0 SLP_S5 = HIGH, SLP_S3 = HIGH, ...
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... Feedback Input Current Oscillator Frequency Oscillator Ramp Amplitude Minimum Duty Cycle Maximum Duty Cycle Soft−Start Pin Current for V1P5 Regulator 4. Guaranteed by design, not tested in production. NCP5220 = 0°C to 70° 1.7 mH, COUT1 = 3770 mF, A Symbol Test Conditions DVTTS0 IOUT 2.0 A (sink current) IOUT – ...
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... A Sourcing Current with 10 ms period and −20 1.0 ms pulse width −21 −22 −23 − AMBIENT TEMPERATURE (°C) A Figure 7. VTT Source Current Load Regulation vs. Ambient Temperature NCP5220 550 500 450 400 350 300 250 200 AMBIENT TEMPERATURE (°C) A Figure 4. Oscillation Frequency in S0/S3 vs. ...
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... Channel 3: VTT Output Voltage, 1.0 V/div Channel 4: V1P5 Output Voltage, 1.0 V/div Time Base: 10 ms/div Figure 11. S0−S5−S0 Transition NCP5220 Channel 1: SLP_S3 Pin Voltage, 5.0 V/div Channel 2: VDDQ Output Voltage, AC−Coupled, 20 mV/div Channel 3: VTT Output Voltage, AC−Coupled, 100 mV/div Channel 4: V1P5 Output Voltage, 50 mV/div Time Base: 10 ms/div Figure 10. S0− ...
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... Channel 4: V1P5 Output Voltage, AC−Coupled, 100 mV/div Time Base: 1.0 ms/div Figure 15. V1P5 Source Current Transient, 0A–12A–0A NCP5220 Channel 1: Current Sourced into V1P5, 10 A/div Channel 2: VDDQ Output Voltage, AC−Coupled, 100 mV/div Channel 3: VTT Output Voltage, AC−Coupled, 100 mV/div V1P5 Output Voltage, AC−Coupled, 100 mV/div Time Base: 1 ...
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... General The NCP5220 3−in−1 PWM Dual Buck Linear DDR Power Controller contains two high efficiency PWM controllers and an integrated two−quadrant linear regulator. The VDDQ supply is produced by a PWM switching controller with two external N−Ch FETs. The VTT termination voltage is an integrated linear regulator with sourcing and sinking current capability which tracks at ½ ...
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... DDQ regulator is in regulation in S0 mode. It draws power from VDDQ with the internal gate drive power derived from 5VDUAL. While VTT output is connecting to the FBVTT NCP5220 pin directly, VTT voltage is designed to automatically track at the half of VDDQ. This regulator is stable with any value of output capacitor greater than 470 mF, and is insensitive to ESR ranging from 400 mW ...
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... V ramps back to regulation. 13 UVLO = L and SLP_S3 = H. MCH ramps with SS pin, timing is 0 14. S0 Mode. 15. S5 Mode −− SLP_S5 = L. 16. DDQ, VTT and MCH Turned OFF. 17. S5 Mode. Figure 17. NCP5220 Power−Up and Power−Down NCP5220 Switching Frequency Doubles 7 ...
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... SLP_S3 = 1 AND SLP_S5 = 1 AND _BOOTGD = 1 NOTE: 5VDUAL is assumed good conditions in any mode. All possible state transitions are shown. All unspecified inputs do not cause any state change. Figure 18. Transitions State Diagram of NCP5220 NCP5220 S5 SLP_S5 = 0 OR (SLP_S3 = 1 AND _BOOTGD = 0) S0 SLP_S3 = 0 AND SLP_S5 = 1 http://onsemi ...
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... The tradeoff is a corresponding increase in the input gate capacitor of the power MOSFETs. PCB Layout Considerations With careful PCB layout the NCP5220 can supply more of current very important to use wide traces or large copper shapes to carry current from the input node through the MOSFET switches, inductor and to the output filters and load ...
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... NCP5220 http://onsemi.com 15 ...
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... Table 2. Bill of Material of NCP5220 Application Circuit Reference Design Description Q1, Q2 Power MOSFET N−Channel Q3, Q4 Power MOSFET N−Channel D1, D2 Rectifier Schottky Diode U1 Controller Zener Zener Diode L1 Toroidal Choke L2, L3 Toroidal Choke C2, C3 Aluminum Electrolytic Capacitor C5 Aluminum Electrolytic Capacitor C21 Aluminum Electrolytic Capacitor ...
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... E2 K 20X 20X 0.10 C 0.05 C BOTTOM VIEW NCP5220 PACKAGE DIMENSIONS MN SUFFIX CASE 505AB−01 ISSUE A NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994 DIMENSIONS IN MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINALS AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS ...
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... USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 18 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NCP5220/D ...