NCP3101 ON Semiconductor, NCP3101 Datasheet - Page 7

• Manufacturer Part Number: NCP3101
• Description: Wide Input Voltage Synchronous Buck Converter
• Manufacturer: ON Semiconductor

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External Soft-Start
which reduces inrush current and overshoot of the output
voltage. Soft-Start is achieved by using the internal current
source of 10 mA (typ) which charges the external integrator
capacitor of the transconductance amplifier. Figure 12 is a
typical soft-start sequence. This sequence begins once V
surpasses its UVLO threshold. During soft-start, as the
Comp Pin rises through 400 mV, the PWM Logic and gate
drives are enabled. When the feedback voltage crosses
800 mV, the EOTA will be given control to switch to its
higher regulation mode output current of 120 mA. In the
event of an over current during the soft-start, the overcurrent
logic will override the soft-start sequence and will shut
down the PWM logic and both the high side and low side
gates of the switching MOSFETS.
UVLO
unexpected behavior does not occur when V
support the internal rails and power the converter. For the
NCP3101, the UVLO is set to ensure that the IC will startup
when V
below 3.6 V. This permits smooth operation from a varying
5.0 V input source.
Current Limit Protection
will conduct large currents. The controller will shut down
the regulator in this situation for protection against
overcurrent. The low side R
comparing the voltage at the phase node when BG starts
going low to an internally generated fixed voltage. If the
phase voltage is lower than OC trip voltage, an overcurrent
condition occurs and a counter is initiated. When the counter
completes, the PWM logic and both HS-FET and LS-FET
are turned off. The converter will reinitialize through the
soft-start cycle to determine if the short circuit or overload
Isource/
Enable
The NCP3101 features an external soft-start function,
V
Undervoltage Lockout (UVLO) is provided to ensure that
In case of a short circuit or overload, the low side LS-FET
comp
Sink
V
fb
CC
Figure 12. Soft-Start Implementation
10 mA
-10 mA
reaches 4.0 V and shutdown when V
Startup
0.4 V
1.1 V
SS
DS(on)
Normal
120 mA
sense is implemented by
CC
0.4 V
10 mA
is too low to
CC
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drops
CC
NCP3101
7
condition has been removed. The minimum turn-on time of
the LS-FET is set to 500 ns. The trip thresholds have a
-95 mV, +45 mV process and temperature variation when
set to -375 mV. The operation of key nodes is displayed in
Figure 13 for both normal operation and during over current
conditions.
Overcurrent Protection Setting
ranging from 50 mV to 550 mV, simply by adding a resistor
(ROCSET) between BG and GND. During a short period of
time following V
10 mA current (IOCSET) is sourced from BG Pin,
determining a voltage drop across ROCSET. This voltage
drop will be sampled and internally held by the device as
Overcurrent Threshold. The OC setting procedure overall
time length is approximately 6 ms. When a ROCSET
resistor is connected between BG and GND, the
programmed threshold is set with an
from 5
OCP threshold to a fixed 375 mV value: an internal safety
clamp on BG is triggered as soon as BG voltage reaches
700 mV, enabling the 375 mV fixed threshold and ending
OC setting phase.
Drivers
Switching MOSFETS with 1 A gate drivers. The gate
drivers also include adaptive nonoverlap circuitry. The
nonoverlap circuitry increase efficiency, which minimizes
power dissipation, by minimizing the body diode
conduction time.
circuitry used in the chip is shown in Figure 14.
SCP Comparated Latch Output
NCP3101 allows the setting of Overcurrent Threshold
In case ROCSET is not connected, the device switches the
The NCP3101 drives the internal High and Low side
A detailed block diagram of the nonoverlap and gate drive
Switch Node Comparator
SCP Trip Voltage
Figure 13. Switching and Current Limit Timing
BO Comparator
kW
IOCth +
HS Gate Drive
LS Gate Drive
Switch Node
to 45
C Phase
2 V
2 V
2 V
CC
kW.
IOCSET * ROCSET
rising over UVLO threshold, an internal
R
DS(on)
RSET values range
(eq. 1)