TDA8961 Philips Semiconductors, TDA8961 Datasheet - Page 17

• Manufacturer Part Number: TDA8961
• Description: ATSC/NTSC digital TV front-end chipset
• Manufacturer: Philips Semiconductors

Philips Semiconductors
E
The I
functions are described in Table 5.
Table 5 I
The TDA8961 I/O and I
ground and 3.3 V. Systems that have devices which
operate at different supply voltages may require special
circuitry to allow these devices to communicate and to be
controlled. Circuit requirements are described in
“Application Report AN97055” (issued Aug. 04, 1997)
available from Philips Semiconductors.
A
The TDA8961 must be addressed by its 7-bit (A6-A0)
slave address sent via the system I
with the correct protocols, and with bit R/W set to either 1
(write data) or 0 (read data).
The slave address of the TDA8961 is given in Table 6.
Bits A6 to A2 are preset, but bits A1 and A0 can be set via
their corresponding external pins.
Table 6 TDA8961 slave address
2000 May 19
SDA
SCL
A0
A1
XTERNAL INTERFACE
DDRESSING THE DEVICE
A6
ATSC Digital Terrestrial TV
demodulator/decoder
0
SIGNAL
2
C-bus external interface has three pins whose
A5
0
2
C-bus external interface
A4
0
I
I
I
I
2
2
2
2
C-bus serial data input/output
C-bus clock input
C-bus slave address input bit 0
C-bus slave address input bit 1
A3
1
2
C-bus signals range between
A2
1
DESCRIPTION
A1
A1
2
C-bus in accordance
A0
A0
0 = write
1 = read
R/W
17
A write operation is shown in Fig.9. The master transmitter
sends a START condition followed by the 7-bit slave
address which is followed by bit R/W set to 0. The slave
receiver (TDA8961) responds by sending an
acknowledge. The master then sends write data starting at
address zero. If the master sends more than one byte of
write data, the TDA8961 automatically increments to the
next address. The TDA8961 sends an acknowledge after
it receives each byte. If the TDA8961 does not
acknowledge the data transfer and/or the master sends a
STOP condition, the data transfer stops. It should be noted
that the TDA8961 does not support I
sub-addressing. Therefore, each I
with the transmission of the slave address and bit R/W,
starts at address zero.
A read operation is shown in Fig.10. The master
transmitter sends a START condition followed by the 7-bit
slave address which is followed by bit R/W set to 1.
The slave receiver (TDA8961) responds by sending an
acknowledge and the value at address zero. The master
responds by sending an acknowledge. If the master
follows the acknowledge with a STOP condition, the data
transfer stops, otherwise the slave is allowed to transfer
more bytes. The slave TDA8961 automatically increments
to the next address of read data to be sent to the master.
2
C-bus transfer starting
Objective specification
2
C-bus
TDA8961