TDA8025 NXP Semiconductors, TDA8025 Datasheet
TDA8025
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TDA8025 Summary of contents
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... Rev. 01 — 6 April 2009 www.datasheet4u.com 1. General description The TDA8025 is a cost-effective analog interface for asynchronous smart cards operating 1 optionally, 1.2 V. Using few external components, the TDA8025 provides integrated supply, protection and control functions for a range of applications. 2. Features I Integrated circuit smart card interface ...
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... I < 200 mA; t < 400 ns CC 1.2 V card: I < single current pulse 100 mA current pulses of 15 nAs with I CC < 200 mA; t < 400 ns pin kHz to 200 MHz CC Rev. 01 — 6 April 2009 TDA8025 IC card interface Min Typ Max 3.6 5 5.5 3 3.3 3.6 [1] 1.6 3.0 3.3 not 1 ...
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... down total sequence +85 C amb for specific limitations on the maximum V Description plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 5 0.85 mm Rev. 01 — 6 April 2009 TDA8025 IC card interface Min Typ Max - - ...
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... XTAL1 AUX1UC XTAL2 I/OUC AUX2UC Rev. 01 — 6 April 2009 TDA8025 IC card interface TEST2 TEST1 TEST4 TEST TEST3 100 DD(INTREGD TDA8025 470 nF 14 CGND LOOP 220 nF 17 RST RESET GENERATOR 15 CLK CLOCK GENERATOR ...
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... LOW 10 I card presence contact input; active HIGH 11 I/O card input/output data line (C7) 12 I/O card auxiliary 2 input/output data line (C8) 13 I/O card auxiliary 1 input/output data line (C4) Rev. 01 — 6 April 2009 TDA8025 IC card interface 24 TEST3 23 OFFN 22 RSTIN 21 V DDI(REG) 20 GND 19 ...
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... I = input output, I/O = input/output ground and P = power supply. [2] If pin PRESN or pin PRES is true, the card is considered to be present. During card insertion, debouncing can occur on these signals. To counter this, the TDA8025 has a built-in debouncing timer (typically 4.5 ms). [3] Using the internal pull-up resistor connected to pin V ...
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... CONFIG pin driven to GND: when V V • CONFIG pin is driven • CONFIG pin is driven The TDA8025 is held in the reset state until V PORADJ V below V All interface signals to the microcontroller are referenced to V contacts remain inactive during power-up and power-down cycles. TDA8025_1 Product data sheet DDI(REG) ...
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... TDA8025 and flawless communication between it and the microcontroller. This information is combined and sent to the digital controller in order to reset the TDA8025. An extension of the power-on reset pulse width of TDA8025 in inactive mode after the supply voltage power on or off sequences (see Figure V (internal signal) Fig 5 ...
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... NXP Semiconductors 8.2.3 V DD(INTREGD) The TDA8025 remains in inactive mode irrespective of the levels on the command lines www.datasheet4u.com when • V • Pin PORADJ (monitoring V In both cases, this lasts for the duration of t and V voltages (V • V for the digital part of the TDA8025 • V information. ...
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... -------------- - 1 + nom R1 nom 1 + -------------------------------------------------- - – -------------- - nom R2 nom is the accuracy ratio of R1 and R2 (R1 and R2 are considered the Rev. 01 — 6 April 2009 TDA8025 V = PORADJ V th max ------------------- - and a maximum value min R1 nom R2 nom max = --------------------------------------- - nom DD INTF actmin ------------------------------------- R2 1 – ...
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... DD INTF deactmax 1 + ------------------------------------- nom , R2 nom 23) then V is 2.28 V. DD(INTF)deactmax 26 MHz) connected between pins XTAL1 and XTAL2. The xtal f . xtal Rev. 01 — 6 April 2009 TDA8025 R sum V DD INTF actmin --------------------------------------- - 1 – max = 100 sum th(max) = 2.64 V then V th min = ------------------ - max below which deactivation always DD(INTF) and ...
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... CLK should be between xtal , xtal CLKDIV1 6 CLKDIV2 5 ENCLKIN 26 (1) External crystal (optional). Clock circuits Figure 8 on page 15 Clock configuration CLKDIV2 Rev. 01 — 6 April 2009 TDA8025 xtal 4 xtal 8 xtal 15 CLK CLOCK CIRCUIT MULTIPLEXER ...
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... Fig 7. 8.5 Inactive mode After a power-on reset, the circuit enters the inactive mode, ensuring only the minimum number of circuits are active while the TDA8025 waits for the microcontroller to start a session. The inactive mode conditions are as follows: • all card contacts are inactive. The impedance between the contacts and GND is approximately 200 . • ...
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... Remark: Do not perform activation with pin RSTIN permanently pulled HIGH. TDA8025_1 Product data sheet Figure rises either from 1 controlled slope (t2) CC and t5 is called t d(start) Rev. 01 — 6 April 2009 TDA8025 IC card interface 8): . d(end) © NXP B.V. 2009. All rights reserved ...
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... Activation sequence: CLK not controlled by pin RSTIN with the crystal oscillator 10): rises either from 1 controlled slope (t2) CC Rev. 01 — 6 April 2009 TDA8025 high frequency d(end) act high frequency d(end) act © ...
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... XTAL1 Rev. 01 — 6 April 2009 TDA8025 IC card interface . f is the low (or inactive mode) d(end) osc(int)low high frequency = t act © NXP B.V. 2009. All rights reserved. ATR 001aai967 ...
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... Fig 11. Activation sequence: CLK not controlled by pin RSTIN and with an external clock 8.7 Active mode When the activation sequence has finished, the TDA8025 is in active mode. This mode enables data exchange between the card and the microcontroller using the input and output lines. ...
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... The deactivation sequence is completed when V CC DD(INTREGD) high frequency t10 t11 t12 t deact Rev. 01 — 6 April 2009 TDA8025 IC card interface Figure 13): using the 11 k resistor low frequency t13 t14 © NXP B.V. 2009. All rights reserved. reaches its CC ...
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... CC buffer has an internal overload protection with a threshold value of 135 mA. CC stability, one 470 nF capacitor should be tied to pin CGND near pin 18 CC falling DD(INTREGD) Rev. 01 — 6 April 2009 TDA8025 IC card interface low frequency t14 t13 1 ...
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... On card insertion or removal, bouncing can occur in the PRES and/or PRESN signals. This depends on the type of card presence switch in the connector (normally open or normally closed) and the mechanical characteristics of the switch. To correct for this, a debouncing feature is integrated in to the TDA8025. This feature operates at a typical duration of 640 ( Remark: f parameter ...
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... Fig 15. Operation of debounce feature pin OFFN in combination with pins CMDVCCN, TDA8025_1 Product data sheet t deb (1) Deactivation caused by card removal. (2) Deactivation caused by short circuit. PRES and V CC Rev. 01 — 6 April 2009 TDA8025 IC card interface t deb (1) © NXP B.V. 2009. All rights reserved. (2) 001aai972 ...
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... Machine Model (MM); all pins; EIA/JESD22-A115-A, October 1997 Charged Device Model (CDM); all pins, except corner pins only corner pins ( 16, 17, 24, 25 and 32) Conditions with exposed pad soldered without exposed pad soldered Rev. 01 — 6 April 2009 TDA8025 IC card interface Min Max Unit 0.3 +5.5 V 0.3 +5 ...
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... 1 1 falling 2.60 DD(INTREGD) pin V ; rising 2.65 DD(INTREGD) pin PORADJ; falling 1.17 pin PORADJ; rising 1.19 pin V 50 DD(INTREGD Rev. 01 — 6 April 2009 TDA8025 IC card interface = 10 MHz; all xtal Typ Max Unit 5 5.5 V 3.3 3.6 V 3.3 3.6 V 3.0 3 0.3 V DDI(REG) 3.3 3 300 ...
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... kHz 200 MHz 1 1 down 0.02 pins XTAL1/XTAL2; - depending on the crystal or resonator specification Rev. 01 — 6 April 2009 TDA8025 IC card interface = 10 MHz; all xtal Typ Max Unit +4 + 830 ...
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... 0.75V OH I < 1 0.75V OH 1.2 V card current limit 0 +1 +1.2 V 0.3 CC 0.6V pin I/O - pin I/ Rev. 01 — 6 April 2009 TDA8025 IC card interface Typ Max - +0.3V DD(INTF DD(INTF) DD(INTF DD(INTF) DD(INTREGD) 0.3 - 200 - 100 - 0.1 - 0.3 ...
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... I/OUC and 8 V DD(INTF) V maximum minimum pF maximum minimum pF Rev. 01 — 6 April 2009 TDA8025 IC card interface Typ Max - 10 - 1.2 - 0.1 - 1 DD(INTF) DD(INTF DD(INTF) DD(INTF DD(INTF) ...
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... [ [ [6] except for xtal L rise and fall pF 1 Rev. 01 — 6 April 2009 TDA8025 IC card interface Typ Max - - 140 200 2.7 3.2 - 0 0.2 0 0.4 - 0.1 - 0.1 - ...
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... V DD(INTREGD) pins PRES and PRESN - DD(INTREGD 0.75V rated at 100 nF and 1 F. DD(INTREGD) Rev. 01 — 6 April 2009 TDA8025 IC card interface Typ Max [7] - +0.3V DD(INTF DD(INTF) DD(INTF) 0.14V - DD(INTF 150 - +0.3V DD(INTF DD(INTREGD) 0.3 0.14V - ...
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... CLK sent to card using an external clock d(start d(end) on pins PRES and PRESN Rev. 01 — 6 April 2009 TDA8025 IC card interface must not exceed DD(INTF) voltage and Table 8 on page 23 DD(INTF) 30; = t1/(t1 + t2). Table 4 on page 12 for pins CLKDIV1 and ; the card is considered as present if at least one of ...
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... NXP Semiconductors www.datasheet4u.com Fig 16. Definition of output and input transition times TDA8025_1 Product data sheet Rev. 01 — 6 April 2009 TDA8025 IC card interface )/ 001aai973 © NXP B.V. 2009. All rights reserved ...
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... Section 8.1 “Power supplies” on page 7 the V restrictions. DD(INTF) DDI(REG) Rev. 01 — 6 April 2009 TDA8025 IC card interface V DD(INTF) TEST3 24 OFFN 23 RSTIN 22 V DDI(REG) 21 TDA8025 GND 20 V DD(INTREGD RST DD(INTREGD) CARD C2 CONNECTOR 220 ...
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... Section 8.1 “Power supplies” on page 7 the V restrictions. DD(INTF) DDI(REG) Rev. 01 — 6 April 2009 TDA8025 IC card interface V DD(INTF) TEST3 24 OFFN 23 RSTIN 22 V DDI(REG) 21 TDA8025 GND 20 V DD(INTREGD RST 470 nF CARD C2 CONNECTOR 220 ...
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... 2.5 scale (1) ( 5.1 3.25 5.1 3.25 0.5 3.5 4.9 2.95 4.9 2.95 REFERENCES JEDEC JEITA MO-220 - - - Rev. 01 — 6 April 2009 TDA8025 IC card interface detail 0.5 0.05 0.1 3.5 0.1 0.05 0.3 EUROPEAN PROJECTION © NXP B.V. 2009. All rights reserved. SOT617-1 c ...
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... Solder bath specifications, including temperature and impurities TDA8025_1 Product data sheet Rev. 01 — 6 April 2009 TDA8025 IC card interface © NXP B.V. 2009. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 20. Rev. 01 — 6 April 2009 TDA8025 IC card interface Figure 20) than a SnPb process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © ...
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... Description Answer To Request ElectroStatic Discharge Equivalent Series Resistance Negative-channel Metal-Oxide Semiconductor Power-On Reset Positive-channel Metal-Oxide Semiconductor Data sheet status Product data sheet Rev. 01 — 6 April 2009 TDA8025 IC card interface peak temperature time 001aac844 Change notice Supersedes - - © NXP B.V. 2009. All rights reserved. ...
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... Export might require a prior authorization from national authorities. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 6 April 2009 TDA8025 IC card interface © NXP B.V. 2009. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com TDA8025 IC card interface All rights reserved. Date of release: 6 April 2009 Document identifier: TDA8025_1 ...