MCP3422A1-E/MS Microchip Technology, MCP3422A1-E/MS Datasheet - Page 26

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MCP3422A1-E/MS

Manufacturer Part Number
MCP3422A1-E/MS
Description
18-Bit, Multi-Channel Delta-Sigma ADC w/ I2C Interface and On-Board Reference ; 8L MSOP 3x3mm
Manufacturer
Microchip Technology
Datasheet
MCP3422/3/4
5.6.5
The
(MCP3422/3/4) use an acknowledge pulse as a hand
shake of communication for each byte. The ninth clock
pulse of each byte is used for the acknowledgement.
The clock pulse is always provided by the Master
(microcontroller) and the acknowledgement is issued
by the receiving device of the byte (Note: The transmit-
ting device must release the SDA line during the
acknowledge
achieved by pulling-down the SDA line “LOW” during
the 9th clock pulse by the receiving device.
FIGURE 5-7:
DS22088B-page 26
SDA
SCL
Master
(A)
ACKNOWLEDGE AND
NON-ACKNOWLEDGE
CONDITION
pulse.).
(microcontroller)
START
(B)
Data Transfer Sequence on I
The
acknowledgement
and
ACKNOWLEDGE
ADDRESS OR
the
VALID
(D)
slave
is
2
C Serial Bus.
TO CHANGE
ALLOWED
DATA
During reads, the Master (microcontroller) can
terminate the current read operation by not providing
an acknowledge bit (not Acknowledge (NAK)) on the
last byte. In this case, the MCP3422/3/4 devices
release the SDA line to allow the Master (microcontrol-
ler) to generate a STOP or repeated START condition.
The non-acknowledgement (NAK) is issued by provid-
ing the SDA line to “HIGH” during the 9th clock pulse.
(D)
© 2008 Microchip Technology Inc.
CONDITION
STOP
(C)
(A)

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