MCP3422A1-E/MS Microchip Technology, MCP3422A1-E/MS Datasheet - Page 19

• Manufacturer Part Number: MCP3422A1-E/MS
• Description: 18-Bit, Multi-Channel Delta-Sigma ADC w/ I2C Interface and On-Board Reference ; 8L MSOP 3x3mm
• Manufacturer: Microchip Technology

If the configuration byte is read repeatedly by clocking
continuously after reading the data bytes (i.e., after the
5th byte in the 18-bit conversion mode), the state of the
RDY bit indicates whether the device is ready with new
conversion result. When the Master finds the RDY bit is
cleared, it can send a not-acknowledge (NAK) bit and
a stop bit to exit the current read operation and send a
new read command for the latest conversion data.
Once the conversion data has been read, the ready bit
toggles to ‘1’ until the next new conversion data is
ready. The conversion data in the output register is
overwritten every time a new conversion is completed.
Figure 5-4
reading the conversion data. The user can rewrite the
configuration byte any time for a new setting.
and
bit operation.
TABLE 5-1:
TABLE 5-2:
© 2008 Microchip Technology Inc.
R/W O/C RDY
R/W O/C RDY
0
0
0
0
1
1
1
1
Table 5-2
0
0
1
1
0
0
1
1
and
show the examples of the configuration
0
1
0
1
0
1
0
1
Figure 5-5
WRITE CONFIGURATION BITS
READ CONFIGURATION BITS
No effect if all other bits remain
the same - operation continues
with the previous settings
Initiate One-Shot Conversion
Initiate Continuous Conversion
Initiate Continuous Conversion
New conversion result in
One-Shot conversion mode has
just been read. The RDY bit
remains low until set by a new
write command.
One-Shot Conversion is in
progress. The conversion result
is not updated yet. The RDY bit
stays high until the current
conversion is completed.
New conversion result in Contin-
uous Conversion mode has just
been read. The RDY bit changes
to high after reading the conver-
sion data.
The conversion result in Continu-
ous Conversion mode was
already read. The next new con-
version data is not ready. The
RDY bit stays high until a new
conversion is completed.
show the examples of
Operation
Operation
Table 5-1
5.3
The device communicates with Master (microcontrol-
ler) through a serial I
face and support standard (100 kbits/sec), fast
(400 kbits/sec) and high-speed (3.4 Mbits/sec) modes.
The serial I
nication protocol using open-drain SCL and SDA lines.
The device can only be addressed as a slave. Once
addressed, it can receive configuration bits with a write
command or transmit the latest conversion results with
a read command. The serial clock pin (SCL) is an input
only and the serial data pin (SDA) is bidirectional. The
Master starts communication by sending a START bit
and terminates the communication by sending a STOP
bit. In read mode, the device releases the SDA line
after receiving NAK and STOP bits.
An example of a hardware connection diagram is
shown in
acteristic is described in Section 5.6 “I
acteristics”.
5.3.1
The first byte after the START bit is always the address
byte of the device, which includes the device code (4
bits), address bits (3 bits), and R/W bit. The device
code for the devices is 1101, which is programmed at
the factory. The I
the MCP3423 and MCP3424 are user configurable and
determined by the logic status of the two external
address selection pins on the user’s application board
(Adr0 and Adr1 pins). The Master must know the Adr0
and Adr1 pin conditions before sending read or write
command.
byte.
The three I
the same I
Master device wants to read the conversion data or
write to the Configuration register. If the (R/W) bit is set
(read mode), the device outputs the conversion data in
the following clocks. If the (R/W) bit is cleared (write
mode), the device expects a configuration byte in the
following clocks. When the device receives the correct
address byte, it outputs an acknowledge bit after the
R/W bit.
Figure 5-1
Figure 5-5
bits and read the conversion results.
I
Figure
2
2
2
2
shows the address byte.
show how to write the configuration register
C Serial Communications
Figure 5-1
C bus line. The (R/W) bit determines if the
I
C address bits allow up to eight devices on
C is a bidirectional 2-wire data bus commu-
2
C DEVICE ADDRESSING
6-1. More details of the I
2
C address bits (A2, A1, A0 bits) for
MCP3422/3/4
2
C (Inter-Integrated Circuit) inter-
shows the details of the address
Figure 5-3
DS22088B-page 19
2
C Bus Char-
2
C bus char-
through