ICL7129 Intersil, ICL7129 Datasheet - Page 5

• Manufacturer Part Number: ICL7129
• Description: 41/2 Digit LCD/ Single-Chip A/D Converter
• Manufacturer: Intersil

Detailed Description
The ICL7129 is a uniquely designed single chip A/D converter.
It features a new “successive integration” technique to achieve
10 V resolution on a 200mV full-scale range. To achieve this
resolution a 10:1 improvement in noise performance over
previous monolithic CMOS A/D converters was accomplished.
Previous integrating converters used an external capacitor to
store an offset correction voltage. This technique worked well
but greatly increased the equivalent noise bandwidth of the
converter. The ICL7129 removes this source of error (noise) by
not using an auto-zero capacitor. Offsets are cancelled using
digital techniques instead. Savings in external parts cost are
realized as well as improved noise performance and elimination
of a source of electromagnetic and electrostatic pick-up.
In the overall Functional Block Diagram of the ICL7129 the
heart of this A/D converter is the sequence counter/decoder
which drives the control logic and keeps track of the many
separate phases required for each conversion cycle. The
sequence counter is constantly running and is a separate
counter from the up/down results counter which is activated
only when the integrator is de-integrating. At the end of a con-
version the data remaining in the results counter is latched,
decoded and multiplexed to the liquid crystal display.
The analog section block diagram shown in Figure 1
includes all of the analog switches used to configure the volt-
age sources and amplifiers in the different phases of the
cycle. The input and reference switching schemes are very
FIGURE 2. INTEGRATOR WAVEFORM FOR NEGATIVE INPUT VOLTAGE SHOWING SUCCESSIVE INTEGRATION PHASES AND
COMMON
IN LO
RESIDUE VOLTAGE
IN HI
ZERO-INTEGRATE
AND LATCH
INT
NOTE: Shaded area greatly expanded
in time and amplitude.
INT
1
, INT
1
DE+
REF HI
DE-
2
DE
C
REF
10,000 CLOCKS
1000 CLOCKS
DE
REF LO
INT
INTEGRATE
DE+
DE-
INT
1
REST, INT
FIGURE 1. ANALOG BLOCK DIAGRAM
+
-
DE-INTEGRATE
BUFFER
Z1, X10
CLOCKS
2
2000
DE
BUFFER
1
R
ICL7129
INT
3-35
REST X10
similar to those in other less accurate integrating A/D con-
verters. There are 5 basic configurations used in the full con-
version cycle. Figure 2 illustrates a typical waveform on the
integrator output. INT, INT
integrate phase where the input voltage is applied to the
integrator amplifier via the buffer amplifier. In this phase, the
integrator ramps over a fixed period of time in a direction
opposite to the polarity of the input voltage.
DE
reference capacitor is switched in series with the buffer ampli-
fier and the integrator ramps back down to the level it started
from before integrating. However, since the de-integrate phase
can terminate only at a clock pulse transition, there is always a
small overshoot of the integrator past the starting point. The
ICL7129 amplifies this overshoot by 10 and DE
larly DE
end of DE 3 the results counter holds a number with 5
of resolution. This was obtained by feeding counts into the
results counter at the 3
digit level during DE
effects of offset in the buffer, integrator, and comparator can
now be cancelled by repeating this entire sequence with the
inputs shorted and subtracting the results from the original
reading. For this phase INT
common-mode voltage as the measurement cycle. This
assures excellent CMRR. At the end of the cycle the data in the
up/down results counter is accurate to 0.02% of full scale and is
sent to the display driver for decoding and multiplexing.
INT, IN
INTEGRATOR
INTEGRATOR
1
C
-
+
VOLTAGE
RESIDUE
, DE
INT
2
DE
’s overshoot is amplified by 10 and DE
2
, and DE
2
INT OUT
1000 CLOCKS
10
100
REST X10
X10
3
2
COMPARATOR 1
are the de-integrate phases where the
1
and the 5
/
+
-
2
DE
digit level during DE
1
2
, and INT
3
switch is closed to give the same
ZERO-INTEGRATE
1
COMPARATOR 2
/
2
+
-
digit level for DE
2
all refer to the signal
TO DIGITAL
SECTION
3
1
2
, into the 4
begins. At the
begins. Simi-
1
/
2
3
. The
digits
1
/
2