SI5110 Silicon Storage Technology Inc, SI5110 Datasheet
SI5110
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SI5110 Summary of contents
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... To simplify BER optimization in long haul applications, programmable slicing, and sample phase adjustment are supported. The Si5110 operates from a single 1.8 V supply over the industrial temperature range (–40°C to 85°C). Functional Block Diagram ...
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Si 5110 2 Preliminary Rev. 0.41 ...
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... Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DSPLL™ Clock Multiplier Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Loop Timed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Diagnostic Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Voltage Reference Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Transmit Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Si5110 Pinout: 99-Pin BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Pin Descriptions: Si5110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Preliminary Rev. 0.41 Si5110 Page 3 ...
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... Table 1. Recommended Operating Conditions Parameter Ambient Temperature LVTTL Output Supply Voltage Si5110 Supply Voltage *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature unless otherwise stated. V ...
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... Figure ISE V 100 Load OH1 Line-to-Line V 100 Load OL1 Line-to-Line V 100 Load OSE Line-to-Line, Figure 1 Preliminary Rev. 0.41 Si5110 80% 20% Min Typ Max Unit — 611 TBD mA — 1.0 TBD W 1.21 1.25 1.29 V TBD 0.1 TBD V 10 — 1.0 mV (pk-pk) ...
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Si 5110 Table 2. DC Characteristics (Continued 1.8 V ±5 –40°C to 85° Parameter LVDS Common Mode Voltage (RXDOUT, RXCLK1, RXCLK2, TXCLK4OUT) Input Impedance (TXDIN, TXCLK4IN, REFCLK, RXDIN) Output Short to GND (RXDOUT, RXCLK1, ...
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... Figure 2 cq1 t Figure 2 cq2 100 kHz–2.5 GHz 2.5 GHz–4.0 GHz SLICELVL = 200–800 mV SLICELVL = 200–800 mV VSLICE PHASEADJ = 200–800 mV LOSLVL = 200–800 mV LOSLVL = 200–800 mV VLOS Preliminary Rev. 0.41 Si5110 Min Typ Max Unit — 622 667 MHz 45 — — 50 — ...
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Si 5110 Table 4. AC Characteristics (TXCLK4OUT, TXCLK4IN, TXCLKOUT, TXDIN, TXDOUT) (V 1.8 V ±5 –40°C to 85° Parameter TXCLKOUT Frequency TXCLKOUT Duty Cycle Output Rise Time (TXCLKOUT, TXDOUT) Output Fall Time (TXCLKOUT, TXDOUT) TXCLKOUT ...
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... DUTY RC TOL LOL LOCK Symbol Test Condition J PRBS 23 GEN(rms) J BWSEL = 0 BW BWSEL = 1 T Valid REFCLK AQ REFRATE = 1 FREQ REFRATE = 0 RC DUTY RC TOL Preliminary Rev. 0.41 Si5110 Min Typ Max Unit 15 30 — UIpp 1.5 3.0 — UIpp 1.5 3.0 — UIpp 0.15 0.3 — UIpp — — — ...
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Si 5110 Table 7. Absolute Maximum Ratings Parameter DC Supply Voltage LVTTL Input Voltage Differential Input Voltages Maximum Current any output PIN Operating Junction Temperature Storage Temperature Range Package Temperature (soldering 10 seconds) ESD HBM Tolerance (100 pf, 1.5 k ...
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... RXCLK2). Sample Phase Adjustment In applications where it is not desirable to recover data by sampling in the center of the data eye, the Si5110 supports adjustment of the CDR sampling phase across the NRZ data period. When sample phase adjustment is enabled, the sampling instant used for data recovery can be moved over a range of ± ...
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... RXCLK1. This clock output is derived by dividing down the recovered clock by a factor of 4. Serial Input to Parallel Output Relationship The Si5110 provides the capability to select the order in which the received serial data is mapped to the parallel output bus RXDOUT[3:0]. The mapping of the receive ...
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... DSPLL transitions from an out of lock state to a locked state (TXLOL transitions from low to high). Parallel Input To Serial Output Relationship The Si5110 provides the capability to select the order in which data on the parallel input bus is transmitted serially. Data on this bus can be transmitted MSB first or LSB first depending on the setting of TXMSBSEL ...
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... When the CDR has locked to the data, RXLOL is driven high. Reset The Si5110 is reset by holding the RESET pin low for at least 1 s. When RESET is asserted low, the input FIFO pointers reset and the digital control circuitry initializes. When RESET transitions high to start normal operation, the CMU will be calibrated ...
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... Transmit Differential Output Circuitry The Si5110 utilizes a current-mode logic (CML) architecture to drive the high speed serial output clock and data on TXCLKOUT and TXDOUT. An example of output termination with ac coupling is shown in Figure 4. In applications where direct dc coupling is possible, the 0.1 F capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is listed in Table 2 on page 5 ...
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... RXDOUT[3] RXMSBSEL REFCLK GND GND REFCLK GND GND TXDIN[2] TXDIN[3] LPTM TXDIN[3] LLBK TXDIN[2] TXDIN[0] TXDIN[1] TXCLKDSBL TXDIN[0] TXDIN[1] TXCLK4IN Figure 5. Si5110 Pin Configuration (Bottom View RXCLK[2] RSVD_GND RXSQLCH RXREXT RXCLK[1] RSVD_GND NC VREF RXCLK2DSBL RSVD_GND RSVD_GND LTR VDD VDD ...
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... GND RESET F TXCLKOUT GND REFRATE G GND VDD33 RSVD_GND H TXDOUT GND RSVD_GND J TXDOUT GND RSVD_GND K GND NC TXREXT Figure 6. Si5110 Pin Configuration (Transparent Top View RXREXT RXSQLCH RSVD_GND RXCLK[2] VREF NC RSVD_GND RXCLK[1] LTR RSVD_GND RSVD_GND RXCLK2DSBL VDD VDD VDD VDD VDD ...
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... Si 5110 Pin Descriptions: Si5110 Pin Name Number(s) H6 BWSEL H7 DLBK J5 FIFOERR H5 FIFORST B2, C2, D1, GND E2, E7–9, F2, F7–9, G1, H2, J2 LLBK D2 LOS B3 LOSLVL 18 I/O Signal Level Bandwidth Select DSPLL. I LVTTL This input selects loop bandwidth of the DSPLL. BWSEL = 0: Loop bandwidth set to 6 kHz. ...
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... MHz or 78 MHz). Reference Clock Select. I LVTTL This input configures the Si5110 to operate with one of two reference clock frequencies. If REFRATE is held high, the device requires a reference clock that is 1/16 the serial data rate. If REFRATE is low, a reference clock at 1/32 the serial data rate is required. ...
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Si 5110 Pin Name Number(s) E3 RESET A6, B6, C5– RSVD_GND 6, D3, G3, H3, J3–4 B7–8 RXCLK1, RXCLK1 C8 RXCLK2DIV C7 RXCLK2DSBL A7–8 RXCLK2, RXCLK2 B1, C1 RXDIN, RXDIN A9–10, B9, RXDOUT[3:0], B10, C9, RXDOUT[3:0] C10, D9, D10 C3 ...
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... High Speed Clock Output. The high speed clock output, TXCLKOUT, is gener- ated by the PLL in the clock multiplier unit. Its fre- quency is nominally 16 times or 32 times the selected reference source. Preliminary Rev. 0.41 Si5110 Description 1 resistor. 21 ...
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... RXLOL, LOS, TXLOL, and FIFOERR are supported. Voltage Reference. O Voltage Ref The Si5110 provides an output voltage reference that can be used by an external circuit to set the LOS threshold, slicing level, or sampling phase adjustment. The equivalent resistance between this pin and GND should not be less than The reference voltage is nominally 1 ...
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... Ordering Guide Part Number Si5110-BC Table 9. Ordering Guide Package Temperature 99 BGA –40°C to 85°C Preliminary Rev. 0.41 Si5110 23 ...
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... Si 5110 Package Outline Figure 7 illustrates the package details for the Si5110. Table 10 lists the values for the dimensions shown in the illustration. A1 Ball Pad Corner D Top View Table 10. Package Diagram Dimensions Seating Plane Side View Figure 7. 99-Ball Grid Array (BGA) ...
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... Preliminary Rev. 0.41 Si5110 25 ...
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Si 5110 Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects ...