IDT70V28L Integrated Device Technology, IDT70V28L Datasheet - Page 14

• Manufacturer Part Number: IDT70V28L
• Description: High-speed 3.3v 64k X 16 Dual-port Static Ram
• Manufacturer: Integrated Device Technology

NOTES:
1. Pins BUSY
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and
3. Writes to the left port are internally ignored when BUSY
4. Refer to Truth Table I - Chip Enable.
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70V28 has an automatic power down
feature controlled by CE. The CE
down circuitry that permits the respective port to go into a standby
mode when not selected (CE = HIGH). When a port is enabled, access
to the entire memory array is permitted.
box or message center) is assigned to each port. The left port interrupt
flag (INT
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V28.
2. There are eight semaphore flags written to via I/O
3. CE = V
No Action
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
CE
IDT70V28L
High-Speed 3.3V 64K x 16 Dual-Port Static RAM
X
X
H
L
pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
enable inputs of this port. If t
BUSY
The IDT70V28 provides two ports with separate control, address
If the user chooses the interrupt function, a memory location (mail
L
R
CE
L
) is asserted when the right port writes to memory location
X
X
H
outputs are driving LOW regardless of actual logic level on the pin.
IH
L
R
, SEM = V
Inputs
L
and BUSY
Functions
NO MATCH
BUSY
A
A
MATCH
MATCH
MATCH
OR
OL
IL
-A
-A
R
to access the semaphores. Refer to Truth Table III - Semaphore Read/Write Control.
15L
15R
are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V28 are push-
APS
is not met, either BUSY
BUSY
0
and CE
(2)
H
H
H
L
Outputs
(1)
1
BUSY
control the on-chip power
D
0
0
and read from all I/O's (I/O
(2)
H
H
H
- D
L
R
outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when
1
1
1
1
1
1
1
L
15
0
0
0
0
(1)
or BUSY
Left
Write Inhibit
Function
R
Normal
Normal
Normal
= LOW will result. BUSY
4849 tbl 17
D
0
- D
(3)
0
15
1
1
1
1
1
1
1
1
-I/O
0
0
0
14
Right
15
FFFE (HEX), where a write is defined as CE
Table IV. The left port clears the interrupt through access of
address location FFFE when CE
Likewise, the right port interrupt flag (INT
port writes to memory location FFFF (HEX) and to clear the interrupt
flag (INT
message (16 bits) at FFFE or FFFF is user-defined since it is an
addressable SRAM location. If the interrupt function is not used, address
locations FFFE and FFFF are not used as mail boxes, but
as part of the random access memory. Refer to Truth Table IV for
the interrupt operation.
). These eight semaphores are addressed by A
Semaphore free
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
L
and BUSY
R
), the right port must read the memory location FFFF. The
R
Industrial and Commercial Temperature Ranges
outputs can not be LOW simultaneously.
L
Status
= OE
0
L
- A
= V
R
2
) is asserted when the left
.
R
IL
= R/W
, R/W is a "don't care".
R
= V
IL
per Truth
4849 tbl 18