IDT71024S Integrated Device Technology, IDT71024S Datasheet - Page 6

• Manufacturer Part Number: IDT71024S
• Description: 128k X 8 Cmos Static Ram With Corner Power & Ground Pinout
• Manufacturer: Integrated Device Technology

Timing Waveform of Write Cycle No. 2
(CS
NOTES:
1. A write occurs during the overlap of a LOW CS
2. t
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS
5. Transition is measured ±200mV from steady state.
6. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, t
Timing Waveform of Write Cycle No. 1
(WE Controlled Timing)
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit)
ADDRESS
ADDRESS
both be active during the t
on the bus for the required t
DATA
WR
DATA
is measured from the earlier of either CS
DATA
1
CS
CS
1
OUT
AND CS
CS
CS
WE
LOW transition or the CS
WE
IN
2
IN
1
2
1
CW
DW
2
write period.
. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified t
Controlled Timing)
2
HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS
t
AS
t
AS
1
or WE going HIGH or CS
1
(3)
, HIGH CS
(1,4,6)
2
, and a LOW WE.
t
t
WHZ
CW
(5)
2
going LOW to the end of the write cycle.
t
t
AW
AW
WP
(1,4)
must be greater than or equal to t
t
t
WP
t
6.42
WC
t
CW
WC
6
(6)
HIGH IMPEDANCE
t
t
DATA
DW
DW
DATA
IN
Commercial and Industrial Temperature Ranges
WHZ
VALID
IN
VALID
+ t
DW
t
DH
t
to allow the I/O drivers to turn off and data to be placed
t
t
WR
WR
OW
(2)
(2)
(5)
t
DH
(3)
t
CHZ
WP
2964 drw 08
1
(5)
2964 drw 07
.
and CS
2
must