IDT7130SA Integrated Device Technology, IDT7130SA Datasheet
IDT7130SA
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IDT7130SA Summary of contents
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... Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin PLCC, and 64-pin STQFP and TQFP Green parts available, see ordering information I/O I/O Control Control MEMORY ARRAY 10 ARBITRATION and INTERRUPT LOGIC 1 IDT7130SA/LA IDT7140SA/ R/W I/O BUSY A 9R Address Decoder ...
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... IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Description The IDT7130/IDT7140 are high-speed Dual-Port Static RAMs. The IDT7130 is designed to be used as a stand-alone 8-bit Dual-Port RAM "MASTER" Dual-Port RAM together with the IDT7140 "SLAVE" Dual-Port in 16-bit-or-more word width systems. ...
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... IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Pin Configurations (1,2,3) 01/08/02 INDEX I/O 0L I/O 1L I/O 2L I/O 3L 01/08/02 INDEX N N/C I/O 0L I/O 1L I/O 2L NOTES: 1. All V pins must be connected to power supply. ...
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... IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Absolute Maximum Ratings Symbol Rating Commercial & Industrial (2) V Terminal Voltage -0.5 to +7.0 TERM with Respect to GND T Temperature -55 to +125 BIAS Under Bias Storage -65 to +150 T STG Temperature I DC Output 50 OUT Current NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...
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... IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter CE and CE I Dynamic Operating CC L Current Outputs Disabled (Both Ports Active) ( MAX CE and CE I Standby Current SB1 L (3) (Both Ports - TTL ...
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... IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Data Retention Characteristics Symbol Parameter V V for Data Retention Data Retention Current CCDR (3) t Chip Deselect to Data Retention Time CDR (3) t Operation Recovery Time R NOTES 2V +25°C, and is not production tested. ...
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... IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 5V DATA OUT 775Ω Figure 1. Output Test Load 5V BUSY or INT Figure 3. BUSY and INT AC Output Test Load Military, Industrial and Commercial Temperature Ranges GND to 3 ...
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... IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range Symbol Parameter READ CYCLE t Read Cycle Time RC t Address Access Time AA t Chip Enable Access Time ACE t Output Enable Access Time AOE t Output Hold from Address Change ...
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... IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Timing Waveform of Read Cycle No. 1, Either Side ADDRESS DATA PREVIOUS DATA VALID OUT BUSY OUT NOTES and Address is valid prior to the coincidental with CE transition LOW delay is required only in the case where the opposite port is completing a write operation to the same the address location. For simultaneous read operations, BDD BUSY has no relationship to valid output data ...
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... IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range Symbol Parameter WRITE CYCLE (3) t Write Cycle Time WC t Chip Enable to End-of-Write EW t Address Valid to End-of-Write AW t Address Set-up Time AS (4) t Write Pulse Width ...
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... IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing) ADDRESS R/W (4) DATA OUT DATA IN Timing Waveform of Write Cycle No. 2, (CE Controlled Timing) ADDRESS CE ( R/W DATA IN NOTES must be HIGH during all address transitions. ...
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... IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol BUSY TIMING (For MASTER IDT 7130) BUSY Access Time from Address t BAA BUSY Disable Time from Address t BDA BUSY Access Time from Chip Enable ...
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... IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Timing Waveform of Write with Port-to-Port Read and BUSY ADDR "A" "A " DATA IN"A" (1) t APS ADDR "B" BUSY "B" DATA OUT"B" NOTES ensure that the earlier of the two ports wins ...
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... IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Timing Waveform of BUSY Arbitration Controlled by CE Timing ADDR AND 'A' 'B' CE 'B' (2) t APS CE 'A' BUSY 'A' Timing Waveform by BUSY Arbitration Controlled by Address Match Timing ADDR ADDRESSES MATCH 'A' (2) t APS ADDR 'B' t BUSY 'B' NOTES: 1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. ...
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... IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM AC Electrical characteristics Over the Operating Temperature and Supply Voltage Range Symbol INTERRUPT TIMING t Address Set-up Time AS t Write Recovery Time WR t Interrupt Set Time INS t Interrupt Reset Time INR NOTES: 1. 'X' in part numbers indicates power rating (SA or LA). ...
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... IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Truth Tables Truth Table I — Non-Contention Read/Write Control (1) Inputs CE OE R DATA DATA NOTES – A • A – 10L 0R 10R 2. If BUSY = L, data is not written. ...
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... IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Functional Description The IDT7130/IDT7140 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7130/IDT7140 has an automatic power down feature controlled by CE. The CE controls on- ...
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... IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Ordering Information XXXX A 999 Device Type Power Speed Package NOTES: 1. Contact your local sales office for industrial temp range for other speeds, packages and powers. 2. Green parts available. For specific speeds, pacakges and powers contact your local sales office. ...
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... IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Datasheet Document History (cont'd) 01/08/02: Page 5, 8, 10, 12, & 14 Page 5, 8, 10, 12, & 14 Page 18 Page 1 & 19 01/11/06: Page 1 Page 18 Page 1 & 19 04/14/06: Page 18 10/21/08: Page 18 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 The IDT logo is a registered trademark of Integrated Device Technology, Inc. ...