UCC1858 Unitrode Semiconductor, UCC1858 Datasheet - Page 4

• Manufacturer Part Number: UCC1858
• Description: High Efficiency, High Power Factor Preregulator
• Manufacturer: Unitrode Semiconductor

PIN DESCRIPTIONS (cont.)
foldback override which enables the part to return quickly
to normal operating mode when the load comes back up.
To override foldback mode, force this pin below 1.5V with
an open collector.
GND: (Ground) All voltages measured with respect to
ground. VDD and VREF should be bypassed directly to
GND with a 0.1 F or larger ceramic capacitor. The timing
capacitor discharge current also returns to this pin, so the
lead from CT to GND should be as short and direct as
possible.
IAC: (Input AC Current) This input to the analog multiplier
is a current. The multiplier is tailored for very low distor-
tion from this current input (IAC) to MOUT. Requires
some bypassing to GND for noise filtering (<470pF).
MOUT: (Multiplier Output) The output of the analog multi-
plier and the non-inverting input of the current amplifier
are connected together at MOUT. As the multiplier output
is a current, this is a high impedance input so the ampli-
fier can be configured as a differential amplifier to reject
ground noise. The voltage at this pin is also used to im-
plement peak current limiting.
OUT: (Gate Drive Output) The output of the PWM is a to-
tem pole MOSFET gate driver. A series gate resistor of at
least 5
the gate impedance and the output driver that might
cause the gate drive to overshoot excessively.
RT: (Oscillator Timing Resistor) A resistor from RT to
GND is used to program oscillator discharge current.
SYNC: (Oscillator Synchronization Input) Allows the PFC
APPLICATION INFORMATION
The UCC3858 is designed to optimize the implementation
of power factor corrected boost converters in low to me-
dium power applications where light load efficiency is
critical. While basic configuration of the UCC3858 is simi-
lar to the industry standard UC3854 series controllers,
several distinguishing features have been added. A typi-
cal application circuit is shown along with a diagram
showing how the UCC3858 can be used with the down-
stream converter to achieve optimum performance.
Chip Bias Supply and Startup
The UCC3858 is implemented using Unitrode’s BCDMOS
process allowing minimal startup (60 A typical) and oper-
ating (3.5mA typical) supply currents. This results in sig-
nificantly lower power consumption in the trickle charge
resistor used to startup the IC, increasing the system effi-
ciency at light loads. Lower supply currents, coupled with
the wide undervoltage lockout hysteresis (13.75V on, 10V
off) provide the opportunity to operate both stages from
is recommended to prevent interaction between
4
to be synchronized to a trailing edge modulator in the
DC-DC stage. A synchronization pulse can be generated
from the positive output edge of the downstream regula-
tor and applied to this pin. The internal clock is reset
(charged up) on the rising edge of the SYNC input.
VA-: (Voltage Amplifier Inverting Input) This pin is nor-
mally connected to the boost converter output through a
divider network. It also is an input to the overvoltage
comparator where by the output is terminated if this pin’s
voltage exceeds 3.15V.
VAO: (Voltage Amplifier Output) Output of the transcon-
ductance amplifier that regulates output voltage. The
voltage amplifier output is internally limited to approxi-
mately 6V for power limiting. It is also used to determine
the frequency foldback mode. Compensation network is
connected from this pin to GND.
VDD: (Positive Supply Voltage) Connect to a stable
source of at least 20mA between 13V and 17V for normal
operation. Bypass VDD directly to GND to absorb supply
current spikes required to charge external MOSFET gate
capacitance. To prevent inadequate gate drive signals,
the output devices will be inhibited unless VDD exceeds
the upper undervoltage lockout voltage threshold and re-
mains above the lower threshold.
VREF: (Reference Voltage) VREF is the output of an ac-
curate 7.5V voltage reference. This output is capable of
delivering 10mA to peripheral circuitry and is internally
short circuit current limited. VREF is disabled and will re-
main at 0V when VDD is low. Bypass VREF to GND with
a 0.1 F or larger ceramic capacitor for best stability.
the same startup and bootstrap supply as shown in the
typical application drawing.
Oscillator and Frequency Foldback at Light Loads
The oscillator of the UCC3858 is set up to operate either
synchronously with the downstream converter or as a
stand alone oscillator. A simplified block diagram of the
oscillator and associated circuitry is shown in Figure 2
and the related waveforms are shown in Figures 3a - 3c.
A rising edge at the SYNC pin initiates the clock cycle by
charging up the CT pin with a nominal internal current of
I
(4.5V) is crossed, the internal latch is set and the CT pin
starts discharging at a rate (I
on the RT pin. In the absence of a SYNC pulse, CT dis-
charges all the way to the ramp low threshold (1V) and
that sets the free running frequency of the oscillator as
given by equation 1. In applications where synchroniza-
tion is used, the RT, CT values should be chosen so that
CHnom
(=19 I
DIS
). Once the high threshold of the ramp
DIS
=3/R
T
) set by the resistor
UCC1858
UCC2858
UCC3858