ACS8525T Semtech, ACS8525T Datasheet - Page 34

• Manufacturer Part Number: ACS8525T
• Description: Line Card Protection Switch for SONET/SDH Systems
• Manufacturer: Semtech

Figure 9 External Sync Input Phase Control (Reg.7B Bits [1:0])
As with all frequencies generated at the outputs of the
ACS8525, the Sync outputs are falling edge aligned.
However, the Sync outputs can be inverted. They can also
be selected to have a number of different pulse widths. In
addition to these controls on the outputs, the input Sync
phases with respect to their associated SEC can be
configured (separately for each Sync). Nominally, the Sync
input is expected to be falling edge aligned with the SEC.
Therefore it is sampled on the rising edge of the SEC. This
gives a tolerance to offset between the SEC and the Sync
input of ±0.5 UI of the SEC clock. If the Sync is delayed or
advanced with respect to the SEC the expected position of
the edge can be moved by 0.5 UI early or late. The
tolerance is always ±0.5 UI of the SEC from the expected
position. Figure 9 summarizes these points and
Sync_phase_SYNC1 (Reg. 7B, Bits [1:0]) provides the
controlling configuration.
Aligning Phase of MFrSync and FrSync Outputs to
Phase of Sync Inputs
The selected Sync input (which is selected by SEC
selection) is monitored by the ACS8525 for consistent
phase and correct frequency compared with the SEC
input, and if it does not pass these quality checks, an
alarm flag is raised (Reg. 08, Bit 7 and Reg. 09, Bit 7). The
check for consistent phase involves checking that each
input edge is within an expected timing window. The
Revision 3.01/August 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
SEC Input
SEC Output
Sync Input
Sync Output
Sync Input
On Target
Sync Input
0.5 UI Early
FINAL
Page 34
window size is set by Reg. 7C, Bits [6:4]. An internal
detector senses that a correct Sync signal is present and
only then allows the signal to resynchronize the internal
dividers that generate the 8 kHz FrSync and 2 kHz
MFrSync outputs. This sequence avoids spurious
resynchronizations that may otherwise occur with
connections and disconnections of the Sync input.
The Sync input will normally be a 2 kHz frequency, only its
falling edge is used. It can however be at a frequencies of
4 kHz or 8 kHz without any change to the register setups.
However the 2 kHz Sync output alignment can only be
achieved when aligning to a 2 kHz SEC.
Safe sampling of the selected Sync input is achieved by
using the “locked-to” SEC, with which it is paired, to do the
input sampling. Phase Build-out mode should be off
(Reg. 48, Bit 2 = 0). The Sync input is normally sampled
on the rising edge of the current input reference clock, in
order to provide the most margin. As mentioned earlier,
modification of the expected timing of the selected Sync
input with respect to its SEC can be achieved via Reg. 7B,
Bits [1:0].
A different sampling resolution is used depending on the
input reference frequency and the setting of Reg. 7B Bit 6,
cnfg_sync_phase. With this bit Low, the Sync input
sampling has a 6.48 MHz resolution. When Bit 6 is High
the selected Sync can have a sampling resolution of
Sync Input
0.5 UI Late
F8525_030ExtSyncPhasCntl_01
ACS8525 LC/P
DATASHEET
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