ACS8525T Semtech, ACS8525T Datasheet - Page 31

• Manufacturer Part Number: ACS8525T
• Description: Line Card Protection Switch for SONET/SDH Systems
• Manufacturer: Semtech

Figure 8 Automatic Mode Control State Diagram (DPLL1)
Note...The state diagram above is for DPLL1 only, and the 3-bit state value refers to the register sts_operating Reg. 09 Bits
[2:0] DPLL1_operating _mode. By contrast, the DPLL2 has only automatic operation and can be in one of only two possible
states: “Instantaneous Automatic Holdover” with zero frequency offset (its start-up state), or “Locked”. The states of DPLL2
are not configurable by the User and there is no “Free-run” state.
Revision 3.01/August 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
(higher-priority ref valid
& in revertive mode) or
(15) valid standby ref
[main ref invalid or
out of lock >100s]
wait for up to 100s
(10) selected source
Pre-locked2
(state 101)
&
phase locked
(higher-priority ref valid
& in revertive mode) or
(4) valid standby ref
out of lock > 100s]
[main ref invalid or
(1) Reset
&
(higher priority ref valid
(12) valid standby ref
or out of lock >100s)
(3) no valid standby ref
& in revertive mode)]
or out of lock > 100s
(9) valid standby ref
[main ref invalid or
(main ref invalid
(main ref invalid
&
&
&
(13) no valid standby ref
(14) all refs evaluated
at least one ref valid
or out of lock >100s)
wait for up to 100s
wait for up to 100s
within 100s
(main ref invalid
(5) selected ref
(8) phase
regained
phase locked
(state 001)
(state 110)
(state 100)
Lost-phase
(state 111)
Pre-locked
select ref
Free-run
keep ref
Locked
&
&
FINAL
Page 31
(7) phase lost
(2) all refs evaluated
at least one ref valid
on main ref
(11) no valid standby ref
or out of lock >100s)
(main ref invalid
&
&
F8525D_018AutoModeContStateDia_01
reference when that reference has lost phase
Reference sources are flagged as valid when
active, in-band and have no phase alarm set.
whilst being used as the main reference. The
A source is considered to have phase locked
when it has been continuously in phase lock
Only the main source is checked for phase.
micro-processor can reset the phase lock
All sources are continuously checked for
(6) no valid standby ref
A phase lock alarm is only raised on a
main ref invalid
Digital Holdover
for between 1 and 2 seconds.
(state 010)
select ref
activity and frequency
&
alarm.
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