ACS-1024-LG Photon Vision Systems, Inc., ACS-1024-LG Datasheet - Page 14

• Manufacturer Part Number: ACS-1024-LG
• Description: Image Sensor, CMOS|CCD, 1026x1026 Pixels, 132pin LCC
• Manufacturer: Photon Vision Systems, Inc.

CONTROL REGISTER 0 and 1 are broken into separate control bits, as described below. Note that some of these bits have a
corresponding I/O pin. The I/O pin is used for the described function whenever the device is in SLAVE mode, otherwise, the
I/O pin is ignored in MASTER mode. See the bond out table above for more information.
CONTROL REGISTER BIT DESCRIPTIONS
REGISTER
CONTROL
0
0
0
0
0
0
0
0
0
0
0
15-1F
10
11
12
13
14
A
B
C
D
5
6
7
8
9
E
F
BIT
10
#
0
1
2
3
4
5
6
7
8
9
Product DATASHEET ACS PDS0003 Subject to change without notice. Page 14 of 26
ROI 1 Row Stop
ROI 1 Col. Start
ROI 1 Col. Stop
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TRANSFER
CONTROL 0
CONTROL 1
ROLLING
HOLDOFF
Reserved
HOLDOFF
G0
G1
F0
F1
SYNC
TM
CS2
CS1
CS2 CS1
1
CS0
CS0 - 0 250us
CS0 - 1 1ms
CDS1
CDS0
NAME
1 – SR4
0 – SR1
1 – SR2
0 – SR3
Full Frame Shutter Mode Holdoff Control Register. This register
Row Address of pixel for ROI 1 to Stop – Must be greater than REG. 4.
Column Address of pixel for ROI 1 to Start – must be less than REG. 7.
Column Address of pixel for ROI 1 to Stop – Must be greater than
REG. 6.
Do not write to this register
Do not write to this register
Do not write to this register
Do not write to this register
Do not write to this register
Do not write to this register
Do not write to this register
Do not write to this register
contains the ‘hold off’ time from the start of the state machine logic
until the pixel site is allowed to accumulate charge. The pixels are held
in reset for this time period. The register default is 0 for full frame
integration.
Transfer Control Register. The charge is transferred from the pixel to
the storage site when the state machine logic reaches the value of this
register. This value must be greater than FFS HOLDOFF
Control Register 0 – See Register 0 bit description, below.
Control Register 1 – See Register 1 bit description, below.
Rolling Shutter mode Holdoff Control Register, controls exposure time
in rolling shutter mode. This register determines the number of rows
back from the current row being read to reset and put back into
integration that row. Units are in rows.
Do not write to these Registers.
See gain and offset table at pin 50
See gain and offset table at pin 50
See gain and offset table at pin 50
See gain and offset table at pin 50
When SYNC bit is set true high state machine waits for sync pulse on pin
58
This register bit has become un-used in the latest revision, the modes
Formerly controlled by this bit are now under the control of the CDS
Bits
Do not write to this bit
CS2 works in conjunction with CS1 to select the system clock speed.
See table below.
Clock Select bit 1, in conjunction with CS2, selects the clock rate for
pixel read out. Frequency is based on 40 MHz Master clock. Frequency
will vary with varying Master clock.
SR1 is 20Mhz. (Master clock/2)
SR2 is 10Mhz. (Master clock/4)
SR3 is 5Mhz. (Master clock/8)
SR4 is 2.5Mhz. (Master clock/16)
CS0 set to 0 selects 250us clock period (4 kHz). Max. integration is 1
second.
CS0 set to 1 selects 1ms clock period (1 kHz). Max. integration is 4
seconds.
See CDS table at pin 40
See CDS table at pin 41
Photon Vision Systems, Inc.
Copyright© 2002 Rev A
DESCRIPTION
0
0
0
0
0
0
0
0
0
0
0
0
0
See Below
See Below
0
0
DEFAULT
0
0
1
1
0
0
0
0
0
0
0