TMP86FS49AFG Toshiba Semiconductor, TMP86FS49AFG Datasheet - Page 156

• Manufacturer Part Number: TMP86FS49AFG
• Description: 8-Bit Microcontroller
• Manufacturer: Toshiba Semiconductor

12.2 Control
12.2 Control
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UART1 Control Register2
UART1 Control Register1
UART1CR2
UART1CR1
(0F96H)
(0F95H)
monitored using the UART status register (UART1SR).
UART1 is controlled by the UART1 Control Registers (UART1CR1, UART1CR2). The operating status can be
Note 1: When operations are disabled by setting TXE and RXE bit to “0”, the setting becomes valid when data transmit or receive
Note 2: The transmit clock and the parity are common to transmit and receive.
Note 3: UART1CR1<RXE> and UART1CR1<TXE> should be set to “0” before UART1CR1<BRG> is changed.
Note: When UART1CR2<RXDNC> = “01”, pulses longer than 96/fc [s] are always regarded as signals; when
UART1CR2<RXDNC> = “10”, longer than 192/fc [s]; and when UART1CR2<RXDNC> = “11”, longer than 384/fc [s].
TXE
complete. When the transmit data is stored in the transmit data buffer, the data are not transmitted. Even if data transmit is
enabled, until new data are written to the transmit data buffer, the current data are not transmitted.
STOPBR
RXDNC
7
7
EVEN
STBT
BRG
TXE
RXE
PE
RXE
6
6
Selection of RXD input noise
rejection time
Receive stop bit length
Transfer operation
Receive operation
Transmit stop bit length
Even-numbered parity
Parity addition
Transmit clock select
STBT
5
5
EVEN
4
4
PE
3
3
2
2
RXDNC
Page 140
000:
001:
010:
100:
101:
011:
110:
111:
00:
01:
10:
11:
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
BRG
1
1
No noise rejection (Hysteresis input)
Rejects pulses shorter than 31/fc [s] as noise
Rejects pulses shorter than 63/fc [s] as noise
Rejects pulses shorter than 127/fc [s] as noise
1 bit
2 bits
Disable
Enable
Disable
Enable
1 bit
2 bits
Odd-numbered parity
Even-numbered parity
No parity
Parity
fc/13 [Hz]
fc/26
fc/52
fc/104
fc/208
fc/416
TC3 ( Input INTTC3)
fc/96
STOPBR
0
0
(Initial value: 0000 0000)
(Initial value: **** *000)
TMP86FS49AFG
Write
Write
only
only