SC28C94 Philips Semiconductors, SC28C94 Datasheet - Page 20

• Manufacturer Part Number: SC28C94
• Description: Quad universal asynchronous receiver/transmitter QUART
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Table 8. Register Bit Formats, I/O Section
IPCR (Input Port Change Register ab) The lower four bits replicate the lower four bits of the IPR. The upper four bits reads change of
state detectors. Change detectors are enabled in ACR[3:0]. (DUART ab)
IPCR (Input Port Change Register cd) The lower four bits replicate the lower four bits of the IPR. The upper four bits reads change of
state detectors. Change detectors are enabled in ACR[3:0]. (DUART cd)
I/OPCR (I/O Port Configuration Register) One register for each UART.
This register controls the configuration of the I/O ports. It defines them as inputs or outputs and controls what sources will drive them in the
case of outputs or which functions they will drive when used as an input. Each pin has four functions and hence two bits to control it. Each
UART has one eight bit register to control its four I/O ports.
OPR (Output Port Register cd) for DUART cd
OPR (Output Port Register ab) for DUART ab
This register contains the data for the I/O ports when they are used as ’General Purpose Outputs’ . The bits of the register are controlled by
writing to the hex addresses at 0C and 1C. Ones written to the OPR drive the pins to 0; zeros drive the pins to 1. (The pins drive the value of
the complement data written to the OPR)
IPR (Input Port Register cd) Reads I/O pins for DUART cd
IPR (Input Port Register ab) Reads I/O pins for DUART ab
This register reads the state of the ’I/O Ports’. The state of the I/O ports is read regardless of being programmed as inputs or outputs.
The IPR can be thought of a just another 8 bit parallel port to the system data bus. The lower four bits of this register are replicated in the lower
four bits of the IPCR register.
I/O Port Control Channel A (IOPCRA)
1998 Aug 19
Bit 7
00 = input
01 = output
10 = output
11 = output
Pin Control Bits
Quad universal asynchronous receiver/transmitter (QUART)
Delta I/O1b
Delta I/O1d
1 = High
1 = High
0 = Low
0 = Low
1 = Yes
1 = Yes
IOPCR[xx]
0 = No
0 = No
I/O3d
I/O3b
I/O3d
I/O3b
I/O3x CONTROL
Bit 6
Delta I/O0b
Delta I/O0d
1 = High
1 = High
0 = Low
0 = Low
IPR(5), TxC in
OPRab(5)
TxC 16x
TxC 1x
1 = Yes
1 = Yes
0 = No
0 = No
I/O2d
I/O2b
I/O2d
I/O2b
IOPCRa[7:6]
One bit for each pin. When I/O pins are configured as “General Purpose Outputs”
One bit for each pin. When I/O pins are configured as “General Purpose Outputs”
I/O3A
the pins will be driven to the complement value of its associated OPR bit.
the pins will be driven to the complement value of its associated OPR bit.
Bit 5
Delta I/O1a
Delta I/O1c
1 = High
1 = High
0 = Low
0 = Low
1 = Yes
1 = Yes
0 = No
0 = No
I/O3a
I/O3c
I/O3a
I/O3c
I/O2x CONTROL
IPR(4), RxC in
OPRab(4)
RTSN
RxC 1x
RxC 16x
Bit 4
Delta I/O0a
Delta I/O0c
1
1 = High
1 = High
0 = Low
0 = Low
1 = Yes
1 = Yes
Two bits for each I/O pin.
0 = No
0 = No
if IOPCR[5:4] = 01
IOPCRa[5:4]
I/O2c
I/O2a
I/O2c
I/O2a
I/O2A
20
Bit 3
1 = High
1 = High
1 = High
1 = High
0 = Low
0 = Low
0 = Low
0 = Low
I/O1b
I/O1b
I/O1d
I/O1d
I/O1b
I/O1d
I/O1x CONTROL
IPR(1), C/Tab Clk in
OPRab(1)
RTSN
RxC 16x
RxC 1x
2
Bit 2
if IOPCR[5:4]
IOPCRa[3:2]
1 = High
1 = High
1 = High
1 = High
0 = Low
0 = Low
0 = Low
0 = Low
I/O1A
I/O0b
I/O0d
I/O0d
I/O0b
I/O0d
I/O0b
1
TxC in
01
Bit 1
1 = High
1 = High
1 = High
1 = High
0 = Low
0 = Low
0 = Low
0 = Low
I/O1a
I/O1c
I/O1c
I/O1a
I/O1c
I/O1a
IPR(0), CTSN
OPRab(0)
TxC 1x
TxC 16x
I/O0x CONTROL
IOPCRa[1:0]
Product specification
SC28C94
I/O0A
Bit 0
1 = High
1 = High
1 = High
1 = High
0 = Low
0 = Low
0 = Low
0 = Low
I/O0a
I/O0c
I/O0c
I/O0a
I/O0c
I/O0a