SC28C94 Philips Semiconductors, SC28C94 Datasheet - Page 14

• Manufacturer Part Number: SC28C94
• Description: Quad universal asynchronous receiver/transmitter QUART
• Manufacturer: Philips Semiconductors

set to MR1 by RESET, a set pointer command applied via the CR or
Philips Semiconductors
Table 4.
ISR (Interrupt Status Register)
IMR (Interrupt Mask Register)
CTUR (Counter/Timer Upper Register)
CTUR (Counter/Timer Lower Register)
IPR (Input Port Register)
Mode Registers 0, 1 and 2
The addressing of the Mode Registers is controlled by the MR
Register pointer. On any access to the Mode Registers this pointer
is always incremented. Upon reaching a value of 2 it remains at 2
until changed by a CR command or a hardware reset.
MR0 – Mode Register 0
Mode Register 0 (MR0) is part of the UART configuration registers.
It controls the watch dog timer and the encoding of the number of
characters received in the RxFIFO. The lower four bits of this
register are not implemented in the hardware of the chip. MR0 is
normally set to either 80h or 00h. A read of this register will return
1111 (Fh) in the lower four bits.
The MR0 register is accessed by setting the MR Pointer to zero (0)
via the command register command 1011 (Bh).
MR0[7]: This bit enables or disables the RxFIFO watch dog timer.
MR0[7] = 1 enable watchdog timer
MR0[7] = 0 disable watchdog timer
MR0[6:4]: These bits are normally set to 0 except as noted in the
“Interrupt Threshold Calculation” description.
MR0[3:0]: These bits are not implemented in the chip. These bits
should be be considered “reserved.”
MR1 – Mode Register 1
MR1 is accessed when the MR pointer points to MR1. The pointer is
after an access to MR0. After reading or writing MR1, the pointers
are set at MR2.
1998 Aug 19
Bit 7
Quad universal asynchronous receiver/transmitter (QUART)
Change
Change
1 = High
I/O Port
I/O Port
0 = Low
1 = Yes
C/T[15]
0 = No
C/T[7]
0 = off
1 = on
I/O3b
INT
Bit 6
Register Bit Formats, Duart ab. [duplicated for Duart cd] (continued)
BREAKb
BREAKb
1 = High
0 = Low
1 = Yes
C/T[14]
0 = No
0 = off
1 = on
C/T[6]
Delta
Delta
I/O2b
INT
Bit 5
RxRDY/
FFULLb
RxRDY/
FFULLb
1 = High
0 = Low
1 = Yes
C/T[13]
0 = No
0 = off
1 = on
C/T[5]
I/O3a
INT
Bit 4
TxRDYb
TxRDYb
1 = High
0 = Low
1 = Yes
C/T[12]
0 = No
0 = off
1 = on
C/T[4]
I/O2a
INT
14
Bit 3
Use of this feature requires the I/O2 pin to be programmed as output
via the I/OPCR and to be driving a 0 via the OPR. When the RxFIFO
MR1[7] – Receiver Request-to-Send Flow Control
This bit controls the deactivation of the RTSN output (I/O2x) by the
receiver. This output is manually asserted and negated by
commands applied via the command register. MR1[7] = 1 causes
RTSN to be automatically negated upon receipt of a valid start bit if
the receiver FIFO is full. RTSN is re-asserted when an empty FIFO
position is available. This feature can be used to prevent overrun in
the receiver by using the RTSN output signal to control the CTS
input (the QUART I/O0 pin) of the transmitting device.
is full and the start bit of the ninth character is sensed the receiver
logic will drive the I/O2 pin high. This pin will return low when
another RxFIFO position is vacant.
MR1[6] – Receiver Interrupt Select 1
This bit is normally set to 0 except as noted in the “Interrupt
Threshold Calculation” description. MR1[6] operates with MR0[6] to
prevent the receiver from bidding until a particular fill level is
attained. For software compatibility this bit is designed to emulate
the RxFIFO interrupt function of previous Philips Semiconductors
UARTs.
MR1[5] – Error Mode Select
This bit selects the operating mode of the three FIFOed status bits
(received break, FE, PE). In the character mode, status is provided
on a character-by-character basis; the status applies only to the
character at the top of the FIFO.
In the block mode, the status provided in the SR for these bits is the
accumulation (logical-OR) of the status for all characters coming to
the top of the FIFO since the last reset error command was issued.
Counter
Counter
1 = High
0 = Low
1 = Yes
C/T[11]
Ready
Ready
0 = No
0 = off
1 = on
C/T[3]
I/O1b
INT
Bit 2
BREAKa
BREAKa
1 = High
0 = Low
1 = Yes
C/T[10]
0 = No
1 = on
C/T[2]
0 = off
I/O0b
Delta
Delta
INT
Bit 1
RxRDY/
FFULLa
RxRDY/
FFULLa
1 = High
0 = Low
1 = Yes
0 = No
0 = off
1 = on
C/T[9]
C/T[1]
I/O1a
INT
Product specification
SC28C94
Bit 0
TxRDYa
TxRDYa
1 = High
0 = Low
1 = Yes
0 = No
C/T[8]
C/T[0]
0 = off
1 = on
I/O0a
INT