STA027 ST Microelectronics, STA027 Datasheet - Page 22

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STA027

Manufacturer Part Number
STA027
Description
SBC Codec
Manufacturer
ST Microelectronics
Datasheet

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5 Register description
5.3.10 PLL_SYSTEM_MDIV_42_5 :
5.4
5.4.1
5.4.2
22/44
Address : 0xEA (234)
Type : RW - DEC
Software Reset : 10
Description :
This register must contain a MDIV value that enables the system PLL to generate a frequency
of 42.5 MHz for the SYSCK.See table 4.
Default value at soft reset assume :
I
OUTPUT_CONF :
Address : 0x66 (102)
Type : RW - DEC
Software Reset : 0
Description :
If set to 1 enable the configurability of the PCM-BLOCK Output thanks to following registers,
else disable this configurability and take embedded default configuration for PCM-BLOCK
registers.
Note that this embedded default configuration can be retrieved by user thanks to following
setting :
PCM_DIV :
Address : 0x67 (103)
Type : RW - DEC
2
Sout_CONFIGURATION registers description
b7
b7
b7
0
external crystal provide a CRYCK running at 14.31818 MHz
PCM_DIV = 3;
PCM_CONF = 0;
PCM_CROSS = 0;
b6
b6
b6
0
DV5
b5
b5
b5
CD00066274
DV4
b4
b4
b4
DV3
b3
b3
b3
DV2
b2
b2
b2
DV1
b1
b1
b1
STA027
DV0
b0
b0
b0

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