T35L6432A-5T Taiwan Memory Technology, Inc., T35L6432A-5T Datasheet - Page 2

• Manufacturer Part Number: T35L6432A-5T
• Description: 64K x 32 SRAM
• Manufacturer: Taiwan Memory Technology, Inc.

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GENERAL DESCRIPTION
chip enable (
(
(
(
global write (
enable (
control (MODE). The data outputs (Q), enabled
by
with either address status processor (
address status controller (
Subsequent burst addresses can be internally
generated as controlled by the burst advance pin
(
registered on-chip to initiate self-timed WRITE
cycle. WRITE cycles can be one to four bytes
FUNCTIONAL BLOCK DIAGRAM
Note: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
A0-A15
MODE
ADSC
ADSP
CE2
ADSC
BW1
ADV
CLK
BW4
BW3
BW2
BW1
ADV
BWE
GW
CE2
CE2
OE
CE
OE
Asynchronous inputs include the output
Addresses and chip enables are registered
Address, data inputs, and write controls are
,
).
, are also asynchronous.
OE
,
BW2
ADSP
descriptions and timing diagrams for detailed information.
16
and
),Snooze enable (ZZ) and burst mode
CH
GW
TE
CE
,
, and
BW3
), depth- expansion chip enables
).
CE2),burst
,
BW4
WRITE REGISTER
WRITE REGISTER
WRITE REGISTER
WRITE REGISTER
ADV
BYTE 4
BYTE 3
BYTE 2
BYTE 1
ADSC
REGISTER
ENABLE
, and
), write enables
REGISTER
ADDRESS
control
) input pins.
CLR
BWE
PIPELINED
ENABLE
(continued)
ADSP
COUNTER
DO D1 Q1
& LOGIC
BINARY
16
A0
), and
inputs
A1
Q0
14
) or
A1'
A0'
8
8
8
8
WRITE DRIVER
WRITE DRIVER
WRITE DRIVER
WRITE DRIVER
16
BYTE 4
BYTE 3
BYTE 2
BYTE 1
P. 2
wide as controlled by the write control inputs.
Individual byte write allows individual byte to be
written.
controls DQ9-DQ16.
24.
bytes to be written.
capability allows written data available at the
output for the immediately next READ cycle.
This device also incorporates pipelined enable
circuit for easy depth expansion without penalizing
system performance.
from a 3.3V +10%/-5% power supply. The device
is ideally suited for Pentium , 680X0, and Power
PC
from a wide synchronous data bus.
BW2
BWE
8
8
8
8
64K x 8 x 4
MEMORY
,
systems and for systems that are benefited
ARRAY
being LOW.
BW4
BW3
4
BW1
32
, and
SENSE
AMPS
controls DQ25-DQ32.
32
controls DQ1-DQ8.
BW4
Publication Date: DEC. 1998
REGISTERS
GW
OUTPUT
The T35L6432A operates
BW3
can be active only with
WRITE pass-through
being LOW causes all
controls DQ17-DQ
BUFFERS
T35L6432A
OUTPUT
REGISTERS
Revision: A
32
INPUT
BW1
BW2
DQ32
DQ1
¡E
¡E
¡E
,