74LVC169BQ,115 NXP Semiconductors, 74LVC169BQ,115 Datasheet
74LVC169BQ,115
Specifications of 74LVC169BQ,115
74LVC169BQ-G
935275616115
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74LVC169BQ,115 Summary of contents
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Presettable synchronous 4-bit up/down binary counter Rev. 05 — 8 June 2009 1. General description The 74LVC169 is a synchronous presettable 4-bit binary counter which features an internal look-ahead carry circuitry for cascading in high-speed counting applications. Synchronous operation ...
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... NXP Semiconductors In order for counting to occur, both pins CEP and CET must be LOW and pin PE must be HIGH. The pin U/D input determines the direction of the counting. The terminal count output pin TC output is normally HIGH and goes LOW, provided that pin CET is LOW, when a counter reaches 15 in the count up mode ...
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... NXP Semiconductors 4. Functional diagram U CEP 10 CET 001aaa645 Fig 1. Logic symbol 74LVC169_5 Product data sheet Presettable synchronous 4-bit up/down binary counter Fig 2. Rev. 05 — 8 June 2009 74LVC169 CTR4 9 M1 [LOAD] M2 [COUNT] M3 [UP [DOWN CT 1, [8] 001aaa646 IEC logic symbol © NXP B.V. 2009. All rights reserved. ...
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... NXP Semiconductors CEP 7 10 CET U/D Fig 3. Logic diagram 74LVC169_5 Product data sheet Presettable synchronous 4-bit up/down binary counter Rev. 05 — 8 June 2009 74LVC169 001aaa649 © NXP B.V. 2009. All rights reserved ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning 74LVC169 U CEP 7 GND 8 001aaa644 Fig 4. Pin configuration SO16 and (T)SSOP16 package 5.2 Pin description Table 2. Pin description Symbol Pin U CEP 7 GND CET 14, 13, 12 74LVC169_5 Product data sheet Presettable synchronous 4-bit up/down binary counter CET ...
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... NXP Semiconductors 6. Functional description [1] Table 3. Function table Operating modes Input CP Parallel load (Dn to Qn) Count up (increment) Count down (decrement) Hold (do nothing) [ HIGH voltage level steady state h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level steady state ...
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... NXP Semiconductors U/D CEP and CET The following sequence is illustrated: - Load (preset) to thirteen. - Count up to fourteen, fifteen (maximum), zero, one and two. - Inhibit. - Countdown to one, zero (minimum), fifteen, fourteen and thirteen. Fig 7. Typical timing sequence 74LVC169_5 Product data sheet Presettable synchronous 4-bit up/down binary counter ...
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... NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK V input voltage I I output clamping current OK V output voltage O I output current ...
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... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V HIGH-level input voltage LOW-level input voltage HIGH-level output I = 100 voltage LOW-level output I = 100 voltage mA mA input leakage V = 3.6 V ...
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... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t propagation delay CP to Qn; see TC; see CET to TC; see U/D to TC; see t pulse width CP HIGH or LOW; see W t set-up time Dn to CP; see ...
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... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions f maximum see max frequency t output skew time V sk( power dissipation per input pin capacitance [1] Typical values are measured the same as t and t ...
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... NXP Semiconductors Measurement points are given in Logic levels: V and Fig 9. Input (CET) to output (TC) propagation delays Measurement points are given in Logic levels: V and Fig 10. The up/down control input (U/D) to output (TC) propagation delays 74LVC169_5 Product data sheet Presettable synchronous 4-bit up/down binary counter ...
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... NXP Semiconductors PE input CP input Dn input The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Logic levels: V and Fig 11. Set-up and hold times for the input (Dn) and parallel enable input (PE) CEP, CET, U/D input CP input The shaded areas indicate when the input is permitted to change for predictable output performance ...
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... NXP Semiconductors Test data is given in Table Definitions for test circuit Load capacitance including jig and probe capacitance Load resistance Termination resistance should be equal to output impedance Z T Fig 13. Test circuit for measuring switching times Table 9. Test data Supply voltage Input V I 1.2 V ...
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... NXP Semiconductors 12. Application information CP U U/D CP CEP TC CET least significant 4-bit counter Fig 14. Synchronous multistage counting scheme 74LVC169_5 Product data sheet Presettable synchronous 4-bit up/down binary counter U/D U CEP TC CEP CET CET Rev. 05 — 8 June 2009 74LVC169 U CEP CET most significant ...
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... NXP Semiconductors 13. Package outline SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors SSOP16: plastic shrink small outline package; 16 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT338-1 Fig 16. Package outline SOT338-1 (SSOP16) ...
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... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been updated and adapted to the new company name where appropriate. • Table 7 “Dynamic characteristics” ECN06_058. ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 6 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 10 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 12 Application information Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 14 Abbreviations ...