TS2GDOM44V-S Transcend Information. Inc., TS2GDOM44V-S Datasheet - Page 26

• Manufacturer Part Number: TS2GDOM44V-S
• Description: Transcend 44-pin Ide Flash Module
• Manufacturer: Transcend Information. Inc.

diagram for the operation is shown in below: Ultra DMA Data-Out Burst Device Termination Timing. The
timing parameters are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are
described in Page 13: Ultra DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
(a) The device shall not initiate Ultra DMA data burst termination until at least one data word of an Ultra
(b) The device shall initiate Ultra DMA data burst termination by negating -DDMARDY.
(c) The host shall stop generating an HSTROBE edges within t
(d) While operating in Ultra DMA modes 2, 1, or 0 the device shall be prepared to receive zero, one or two
(e) The device shall negate DMARQ no sooner than t
(f) The host shall assert STOP within t
(g) If HSTROBE is negated, the host shall assert HSTROBE within t
(h) The host shall place the result of its CRC calculation on D[15:00] (see ATA specification Ultra DMA
(i) The host shall negate -DMACK no sooner than t
(j) The device shall latch the host’s CRC data from D[15:00] on the negating edge of -DMACK.
(k) The device shall compare the CRC data received from the host with the results of its own CRC
(l) While operating in True IDE mode, the device shall release DSTROBE within t
(m) The host shall not negate STOP nor assert –HDMARDY until at least t
(n) In True IDE mode, the host shall not assert -IOWR, -CS0, -CS1, nor A[02:00] until at least t
The device terminates an Ultra DMA Data-Out burst by following the steps lettered below. The timing
Device Terminating an Ultra DMA Data-Out Burst
assert DMARQ again until after the Ultra DMA data burst is terminated.
STOP again until after the Ultra DMA data burst is terminated.
DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition of
HSTROBE. HSTROBE shall remain asserted until the Ultra DMA data burst is terminated.
CRC Calculation).
and the device has negated DMARQ and -DDMARDY, and no sooner than t
of its CRC calculation on D[15:00].
calculation. If a miscompare error occurs during one or more Ultra DMA data bursts for any one
command, the device shall report the first error that occurred (see ATA specification Ultra DMA CRC
Calculation).
negates -DMACK.
negating DMACK.
Transcend Information Inc.
DMA data burst has been transferred.
additional data words after negating -HDMARDY. While operating in Ultra DMA modes 4 or 3 the
device shall be prepared to receive zero, one, two or three additional data words. The additional
data words are a result of cable round trip delay and t
T
T
T
r
r
r
a
a
a
n
n
n
s
s
s
c
c
T
c
T
T
e
e
e
S
S
S
n
n
n
1
1
1
d
d
d
2
2
2
8
8
8
4
4
4
M
M
M
4
4
4
-
-
-
P
P
~
P
~
~
i
i
i
8
n
n
8
n
8
G
G
G
LI
I
I
I
D
D
D
D
D
after the device has negated DMARQ. The host shall not negate
D
E
E
E
O
O
O
M
F
F
M
F
M
l
l
l
4
4
a
a
4
a
4
s
4
s
4
s
MLI
26
V
h
V
h
V
h
RP
-
-
-
after the host has asserted HSTROBE and STOP
M
M
S
S
M
S
after negating -DDMARDY. The device shall not
o
o
o
RFS
d
d
d
u
u
u
timing for the device.
RFS
l
l
l
e
e
e
of the device negating -DDMARDY.
LI
after the device has negated
ACK
DVS
after negating -DMACK.
IORDYZ
after placing the result
after the host
ACK
Ver 1.2
after