RC28F256P33TF Numonyx, RC28F256P33TF Datasheet - Page 53

• Manufacturer Part Number: RC28F256P33TF
• Description: 256-mbit, 512-mbit 256m/256m
• Manufacturer: Numonyx

P33-65nm
Figure 20: Synchronous Single-Word Array or Non-array Read Timing
Notes:
1.
2.
Figure 21: Continuous Burst Read, showing an Output Delay Timing
Notes:
1.
2.
Datasheet
53
Address [A]
Data [D/Q]
ADV# [V]
WAIT [T]
WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either
during or one data cycle before valid data.
This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by
CE# deassertion after the first word in the burst.
WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either
during or one data cycle before valid data.
At the end of Word Line; the delay incurred when a burst access crosses a 16-word boundary and the starting address is
not 4-word boundary aligned. See
page 37
OE# [G]
CLK [C]
CE# [E]
Address [A]
Data [D/Q]
ADV# [V]
WAIT [T]
OE# [G]
CLK [C]
CE# [E]
.
for more information
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Section 11.1.3, “End of Word Line (EOWL) Considerations” on
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Order Number:320003-05
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Nov 2008