RC28F256P33TF Numonyx, RC28F256P33TF Datasheet - Page 38

• Manufacturer Part Number: RC28F256P33TF
• Description: 256-mbit, 512-mbit 256m/256m
• Manufacturer: Numonyx

Table 13: End of Wordline Data and WAIT state Comparison
11.1.4
11.1.5
Datasheet
38
Latency Count
10
11
12
13
14
15
1
2
3
4
5
6
7
8
9
WAIT Polarity
The WAIT Polarity bit (WP), RCR.10 determines the asserted level (V
When WP is set, WAIT is asserted high. When WP is cleared, WAIT is asserted low
(default). WAIT changes state on valid clock edges during active bus cycles (CE#
asserted, OE# asserted, RST# deasserted).
WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous mode
(RCR.15=0). The WAIT signal is only “deasserted” when data is valid on the bus.
When the device is operating in synchronous non-array read mode, such as read
status, read ID, or read query. The WAIT signal is also “deasserted” when data is valid
on the bus.
WAIT behavior during synchronous non-array reads at the end of word line works
correctly only on the first data access.
When the device is operating in asynchronous page mode, asynchronous single word
read mode, and all write operations, WAIT is set to a deasserted state as determined
by RCR.10. See
page
52, and
Not Supported
Not Supported
Data States
Figure 19, “Asynchronous Page-Mode Read Timing” on page
4
4
4
4
4
4
Figure 18, “Asynchronous Single-Word Read (ADV# Latch)” on
P33-130nm
Not Supported
Not Supported
WAIT States
0 to 1
0 to 2
0 to 3
0 to 4
0 to 5
0 to 6
Not Supported
Not Supported
Data States
16
16
16
16
16
16
16
16
16
16
16
16
16
P33-65nm
Order Number: 320003-05
OH
or V
Not Supported
Not Supported
WAIT States
0 to 10
0 to 11
0 to 12
0 to 13
0 to 14
52.
OL
0 to 2
0 to 3
0 to 4
0 to 5
0 to 6
0 to 7
0 to 8
0 to 9
) of WAIT.
P33-65nm
Nov 2008