ISL95711 Intersil Corporation, ISL95711 Datasheet - Page 7

• Manufacturer Part Number: ISL95711
• Description: 128 Taps I2C Serial Interface
• Manufacturer: Intersil Corporation

Test Circuit
Equivalent Circuit
Pin Descriptions
Potentiometer Pins
R
The high (R
equivalent to the fixed terminals of a mechanical
potentiometer. R
position of the wiper and not the voltage potential on the
terminals. With WR set to 127, the wiper will be closest to
R
R
R
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WR.
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin for the
I
wiper register address and data from a I
device at the rising edge of the serial clock SCL, and it shifts
out data after each falling edge of the serial clock SCL.
SDA requires an external pull-up resistor, since it’s an open
drain input/output.
SERIAL CLOCK (SCL)
This input is the serial clock of the I
SCL requires an external pull-up resistor, since it’s an open
drain input.
DEVICE ADDRESS (A1-A0)
The Address inputs are used to set the least significant 2 bits
of the 7-bit I
2
H
H
W
w
C interface. It receives device address, operation code,
, and with the WR set to 00, the wiper is closest to R
AND R
is the wiper terminal and is equivalent to the movable
L
H
2
R
C interface slave address. A match in the slave
H
) and low (R
H
and R
C
H
H
L
) terminals of the ISL95711 are
R
are referenced to the relative
TOTAL
R
R
W
7
W
TEST POINT
C
FORCE
CURRENT
W
2
C serial interface.
2
C external master
C
L
R
L
L
ISL95711
address serial data stream must be made with the Address
input pins in order to initiate communication with the
ISL95711. A maximum of 4 ISL95711 devices may occupy
the I
Principles of Operation
The ISL95711 is an integrated circuit incorporating one DCP
with it’s associated register, non-volatile memory, and the
I
a host and the potentiometer and memory. The resistor array
is comprised of individual resistors connected in series. At
either end of the array and between each resistor is an
electronic switch that transfers the potential at that point to
the wiper.
The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
When the device is powered-down, the last value stored in
the IVR will be maintained in the nonvolatile memory. When
power is restored, the contents of the IVR are recalled and
the wiper is set to that value.
The ISL95711 has dual supplies, V
operation of the chip, it is recommended both power
supplies ramp up simultaneously to their final values within
20ms. The chip design gives priority to the V- supply
stabilization and then looks at V
supply goes below -2.5V, the R
code of 64. As V
R
value (this is referred as power on recall).
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of the
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (R
intermediate nodes, and is equivalent to the wiper terminal
of a mechanical potentiometer. The position of the wiper
terminal is controlled by a 7-bit volatile Wiper Register (WR).
When the WR contains all zeroes (00h), the wiper terminal
(R
contains all ones (7Fh), the wiper terminal (R
its “High” terminal (R
from all zeroes (00h) to all ones (7Fh), the wiper moves
monotonically from the position closest to R
closest to R
and R
between R
While the ISL95711 is being powered up, the WR is reset to
40h (64 decimal), which locates the R
2
W
C serial interface providing direct communication between
W
pin goes to the code stored in the EEPROM memory
) is closest to its “Low” terminal (R
2
C serial bus.
L
increases monotonically, while the resistance
H
H
and R
. At the same time, the resistance between R
CC
H
and R
W
also exceeds 2.5V (after V- < -2.5V), the
H
decreases monotonically.
). As the value of the WR increases
L
pins). The R
W
CC
pin goes to the default
CC
stabilization. As the V-
W
L
and V-. For proper
W
). When the WR
at the center
pin is connected to
L
W
to the position
) is closest to
August 15, 2005
FN8241.2
W